diff for duplicates of <53FEE9E6.2000204@arm.com> diff --git a/a/1.txt b/N1/1.txt index 6bd7c8e..b80f457 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -69,7 +69,7 @@ On 28/08/14 04:56, Olof Johansson wrote: >> + mshc2 = &mmc_2; >> + }; >> + ->> + chipid@10000000 { +>> + chipid at 10000000 { >> + compatible = "samsung,exynos4210-chipid"; >> + reg = <0x10000000 0x100>; >> + }; @@ -80,7 +80,7 @@ On 28/08/14 04:56, Olof Johansson wrote: > > Why size-cells=2? Can you not fit a cpuid in 32 bits? > ->> + cpu@0 { +>> + cpu at 0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a57", "arm,armv8"; >> + reg = <0x0 0x0>; @@ -94,7 +94,7 @@ On 28/08/14 04:56, Olof Johansson wrote: >> + #clock-cells = <0>; >> + }; >> + ->> + gic: interrupt-controller@11001000 { +>> + gic: interrupt-controller at 11001000 { >> + compatible = "arm,gic-400"; >> + #interrupt-cells = <3>; >> + #address-cells = <0>; @@ -105,7 +105,7 @@ On 28/08/14 04:56, Olof Johansson wrote: >> + <0x11006000 0x2000>; >> + }; >> + ->> + hsi2c_0: hsi2c@13640000 { +>> + hsi2c_0: hsi2c at 13640000 { >> + compatible = "samsung,exynos7-hsi2c"; > > Is the i2c controller here completely new? @@ -123,7 +123,7 @@ On 28/08/14 04:56, Olof Johansson wrote: >> + status = "disabled"; >> + }; >> + ->> + hsi2c_1: hsi2c@13650000 { +>> + hsi2c_1: hsi2c at 13650000 { >> + compatible = "samsung,exynos7-hsi2c"; >> + reg = <0x13650000 0x1000>; >> + interrupts = <0 442 0>; @@ -136,19 +136,19 @@ On 28/08/14 04:56, Olof Johansson wrote: >> + status = "disabled"; >> + }; >> + ->> + hsi2c_2: hsi2c@14E60000 { +>> + hsi2c_2: hsi2c at 14E60000 { > > I much prefer lowercase hex in unit addresses (and reg entries) below. I > know 32-bit uses uppercase, but let's switch going forward here. > ->> + mct@101C0000 { +>> + mct at 101C0000 { >> + compatible = "samsung,exynos4210-mct"; > > Please just do away with MCT here, and use architected timers going > forward. There really shouldn't be a need to keep supporting MCT any > more -- it's a construct from before arch timers on Cortex-A9. > ->> + mmc_0: mmc@15740000 { +>> + mmc_0: mmc at 15740000 { >> + compatible = "samsung,exynos7-dw-mshc-smu"; > > Is this controller backwards compatible with exynos5 ones? diff --git a/a/content_digest b/N1/content_digest index 75cef43..475d944 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,19 +1,10 @@ "ref\01409132660-1898-1-git-send-email-ch.naveen@samsung.com\0" "ref\01409132660-1898-3-git-send-email-ch.naveen@samsung.com\0" "ref\020140828035639.GB4972@localhost\0" - "From\0Marc Zyngier <marc.zyngier@arm.com>\0" - "Subject\0Re: [PATCH 11/14] arm64: dts: Add initial device tree support for EXYNOS7\0" + "From\0marc.zyngier@arm.com (Marc Zyngier)\0" + "Subject\0[PATCH 11/14] arm64: dts: Add initial device tree support for EXYNOS7\0" "Date\0Thu, 28 Aug 2014 09:35:50 +0100\0" - "To\0Olof Johansson <olof@lixom.net>" - " Naveen Krishna Chatradhi <ch.naveen@samsung.com>\0" - "Cc\0devicetree@vger.kernel.org <devicetree@vger.kernel.org>" - linux-samsung-soc@vger.kernel.org <linux-samsung-soc@vger.kernel.org> - Rob Herring <robh@kernel.org> - Catalin Marinas <Catalin.Marinas@arm.com> - Thomas Abraham <thomas.ab@samsung.com> - cpgs@samsung.com <cpgs@samsung.com> - naveenkrishna.ch@gmail.com <naveenkrishna.ch@gmail.com> - " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 28/08/14 04:56, Olof Johansson wrote:\n" @@ -87,7 +78,7 @@ ">> +\t\tmshc2 = &mmc_2;\n" ">> +\t};\n" ">> +\n" - ">> +\tchipid@10000000 {\n" + ">> +\tchipid at 10000000 {\n" ">> +\t\tcompatible = \"samsung,exynos4210-chipid\";\n" ">> +\t\treg = <0x10000000 0x100>;\n" ">> +\t};\n" @@ -98,7 +89,7 @@ "> \n" "> Why size-cells=2? Can you not fit a cpuid in 32 bits?\n" "> \n" - ">> +\t\tcpu@0 {\n" + ">> +\t\tcpu at 0 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"arm,cortex-a57\", \"arm,armv8\";\n" ">> +\t\t\treg = <0x0 0x0>;\n" @@ -112,7 +103,7 @@ ">> +\t\t#clock-cells = <0>;\n" ">> +\t};\n" ">> +\n" - ">> +\tgic: interrupt-controller@11001000 {\n" + ">> +\tgic: interrupt-controller at 11001000 {\n" ">> +\t\tcompatible = \"arm,gic-400\";\n" ">> +\t\t#interrupt-cells = <3>;\n" ">> +\t\t#address-cells = <0>;\n" @@ -123,7 +114,7 @@ ">> +\t\t\t<0x11006000 0x2000>;\n" ">> +\t};\n" ">> +\n" - ">> +\thsi2c_0: hsi2c@13640000 {\n" + ">> +\thsi2c_0: hsi2c at 13640000 {\n" ">> +\t\tcompatible = \"samsung,exynos7-hsi2c\";\n" "> \n" "> Is the i2c controller here completely new?\n" @@ -141,7 +132,7 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\thsi2c_1: hsi2c@13650000 {\n" + ">> +\thsi2c_1: hsi2c at 13650000 {\n" ">> +\t\tcompatible = \"samsung,exynos7-hsi2c\";\n" ">> +\t\treg = <0x13650000 0x1000>;\n" ">> +\t\tinterrupts = <0 442 0>;\n" @@ -154,19 +145,19 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\thsi2c_2: hsi2c@14E60000 {\n" + ">> +\thsi2c_2: hsi2c at 14E60000 {\n" "> \n" "> I much prefer lowercase hex in unit addresses (and reg entries) below. I\n" "> know 32-bit uses uppercase, but let's switch going forward here.\n" "> \n" - ">> +\tmct@101C0000 {\n" + ">> +\tmct at 101C0000 {\n" ">> +\t\tcompatible = \"samsung,exynos4210-mct\";\n" "> \n" "> Please just do away with MCT here, and use architected timers going\n" "> forward. There really shouldn't be a need to keep supporting MCT any\n" "> more -- it's a construct from before arch timers on Cortex-A9.\n" "> \n" - ">> +\tmmc_0: mmc@15740000 {\n" + ">> +\tmmc_0: mmc at 15740000 {\n" ">> +\t\tcompatible = \"samsung,exynos7-dw-mshc-smu\";\n" "> \n" "> Is this controller backwards compatible with exynos5 ones?\n" @@ -206,4 +197,4 @@ "-- \n" Jazz is not dead. It just smells funny... -f7f02eafb6901e3eae508f04e65c2be528320d2c8f7a12c60b9d36851d01aefd +dfb7d1266c3fa6d15c9359aeff6e68d0d42ce031332f607020b416bf4f497820
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.