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From: Deepak S <deepak.s@linux.intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 2/4] drm/i915: Populate mem_freq in init_gt_powerwave()
Date: Thu, 28 Aug 2014 21:39:28 +0530	[thread overview]
Message-ID: <53FF5438.3080909@linux.intel.com> (raw)
In-Reply-To: <1408362166-5856-3-git-send-email-ville.syrjala@linux.intel.com>


On Monday 18 August 2014 05:12 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> init_clock_gating() is too late to read out the mem_freq. We already
> want to print out the GPU MHz numbers before it's called. Move the
> mem_freq setup to init_gt_powersave().
>
> v2: Also kill the CHV_CZ_CLOCK_FREQ_MODE_* defines
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h |  6 ---
>   drivers/gpu/drm/i915/intel_pm.c | 90 ++++++++++++++++++++---------------------
>   2 files changed, 43 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 203062e..2df946d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5650,12 +5650,6 @@ enum punit_power_well {
>   						 GEN6_PM_RP_DOWN_THRESHOLD | \
>   						 GEN6_PM_RP_DOWN_TIMEOUT)
>   
> -#define CHV_CZ_CLOCK_FREQ_MODE_200			200
> -#define CHV_CZ_CLOCK_FREQ_MODE_267			267
> -#define CHV_CZ_CLOCK_FREQ_MODE_320			320
> -#define CHV_CZ_CLOCK_FREQ_MODE_333			333
> -#define CHV_CZ_CLOCK_FREQ_MODE_400			400
> -
>   #define GEN7_GT_SCRATCH_BASE			0x4F100
>   #define GEN7_GT_SCRATCH_REG_NUM			8
>   
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c84ad93..39dd066 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4088,11 +4088,27 @@ static void valleyview_cleanup_pctx(struct drm_device *dev)
>   static void valleyview_init_gt_powersave(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 val;
>   
>   	valleyview_setup_pctx(dev);
>   
>   	mutex_lock(&dev_priv->rps.hw_lock);
>   
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	switch ((val >> 6) & 3) {
> +	case 0:
> +	case 1:
> +		dev_priv->mem_freq = 800;
> +		break;
> +	case 2:
> +		dev_priv->mem_freq = 1066;
> +		break;
> +	case 3:
> +		dev_priv->mem_freq = 1333;
> +		break;
> +	}
> +	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
> +
>   	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
>   	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>   	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> @@ -4127,11 +4143,38 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
>   static void cherryview_init_gt_powersave(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 val;
>   
>   	cherryview_setup_pctx(dev);
>   
>   	mutex_lock(&dev_priv->rps.hw_lock);
>   
> +	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
> +	switch ((val >> 2) & 0x7) {
> +	case 0:
> +	case 1:
> +		dev_priv->rps.cz_freq = 200;
> +		dev_priv->mem_freq = 1600;
> +		break;
> +	case 2:
> +		dev_priv->rps.cz_freq = 267;
> +		dev_priv->mem_freq = 1600;
> +		break;
> +	case 3:
> +		dev_priv->rps.cz_freq = 333;
> +		dev_priv->mem_freq = 2000;
> +		break;
> +	case 4:
> +		dev_priv->rps.cz_freq = 320;
> +		dev_priv->mem_freq = 1600;
> +		break;
> +	case 5:
> +		dev_priv->rps.cz_freq = 400;
> +		dev_priv->mem_freq = 1600;
> +		break;
> +	}
> +	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
> +
>   	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
>   	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
>   	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> @@ -5760,24 +5803,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>   static void valleyview_init_clock_gating(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->rps.hw_lock);
> -	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> -	mutex_unlock(&dev_priv->rps.hw_lock);
> -	switch ((val >> 6) & 3) {
> -	case 0:
> -	case 1:
> -		dev_priv->mem_freq = 800;
> -		break;
> -	case 2:
> -		dev_priv->mem_freq = 1066;
> -		break;
> -	case 3:
> -		dev_priv->mem_freq = 1333;
> -		break;
> -	}
> -	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>   
>   	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>   
> @@ -5853,35 +5878,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>   static void cherryview_init_clock_gating(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 val;
> -
> -	mutex_lock(&dev_priv->rps.hw_lock);
> -	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
> -	mutex_unlock(&dev_priv->rps.hw_lock);
> -	switch ((val >> 2) & 0x7) {
> -	case 0:
> -	case 1:
> -			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
> -			dev_priv->mem_freq = 1600;
> -			break;
> -	case 2:
> -			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
> -			dev_priv->mem_freq = 1600;
> -			break;
> -	case 3:
> -			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
> -			dev_priv->mem_freq = 2000;
> -			break;
> -	case 4:
> -			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
> -			dev_priv->mem_freq = 1600;
> -			break;
> -	case 5:
> -			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
> -			dev_priv->mem_freq = 1600;
> -			break;
> -	}
> -	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>   
>   	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>   

Patch looks fine to me
Reviewed-by: Deepak S<deepak.s@linux.intel.com>


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  reply	other threads:[~2014-08-27 16:14 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-18 11:42 [PATCH 0/4] drm/i915: A few CHV stragglers ville.syrjala
2014-08-18 11:42 ` [PATCH 1/4] drm/i915: Warn about odd rps values on CHV ville.syrjala
2014-08-28 16:06   ` Deepak S
2014-08-18 11:42 ` [PATCH v2 2/4] drm/i915: Populate mem_freq in init_gt_powerwave() ville.syrjala
2014-08-28 16:09   ` Deepak S [this message]
2014-08-18 11:42 ` [PATCH 3/4] drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv ville.syrjala
2014-10-02 13:53   ` Mika Kuoppala
2014-08-18 11:42 ` [PATCH v2 4/4] drm/i915: Clear TX FIFO reset master override " ville.syrjala
2014-10-02 14:33   ` Mika Kuoppala
2014-10-03  8:21     ` Daniel Vetter

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