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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-482e28f854dsm8106335f8f.36.2026.08.27.03.31.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Aug 2026 03:31:59 -0700 (PDT) Message-ID: <53ce22e0-a26e-4641-ba20-0ae65b290bc7@oss.qualcomm.com> Date: Thu, 27 Aug 2026 12:31:57 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/4] Rename ssi_transfer to ssi_transfer8 Content-Language: en-US To: Alistair , stephensportia@gmail.com, qemu-devel@nongnu.org, Bin Meng Cc: Palmer Dabbelt , Peter Maydell , Jamin Lin , qemu-ppc@nongnu.org, =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Steven Lee , Andrew Jeffery , Harsh Prateek Bora , Subbaraya Sundeep , Troy Lee , "Edgar E. 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All child classes of SSI_PERIPHERAL class >> have >> transfer functions that, despite accepting a 32-bit tx, only transfer >> a >> single byte; m25p80_transfer8(), ssi_sd_transfer(), >> ssd0323_transfer(). >> >> The current implementation depends on the SSI model to know >> what peripheral model will be attached and what transfer size it >> expects which is error prone. If a SSI_PERIPHERAL model was written >> that >> accepted 32-bit transfers, it could not attach to any existing SSI >> models. >> >> This change updates the the naming of ssi_transfer to ssi_transfer8, >> as >> well as changes the return value and transmit argument to be 8-bit. >> >> Most ssi models handle this correctly already, sending a single byte >> at >> a time. There are a few models that are written to support non 8-bit >> transfers but there are no in-tree use cases that connect a >> peripheral >> to the SSI device. These have been updated to use 8-bit transfers. >> >> Portia Stephens (4): >>   hw/ssi: Rename ssi_transfer to ssi_transfer8 >>   hw/ssi/pl022: Fix dropped upper bytes of ssi transfer >>   hw/arm/strongarm: Fix dropped upper byte of ssi transfer >>   hw/ssi/pnv_spi: Fix dropped upper bytes of ssi transfer > > Thanks! > > Applied to riscv-to-apply.next Can you hold on before merging this please (or drop it from your riscv queue)? I tagged this series to review but didn't got a sufficient large enough slot to look at it. In short, the reason I think this isn't the correct way to go is SPI "words" can be any number of bits. While QEMU only models 8-bit word devices, I have be working with 16-bit and even 24-bit words ones, so I believe the current implementation is right. I have be thinking of a better way to model this granularity in our class hooks, but haven't find a good one yet. Restricting some devices to 8-bit to simplify them move part of the complexity to the host controller so I'm not sure it is useful. I'll return with clearer comments when I get more time. Thanks, Phil.