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([2001:b07:add:ec09:c399:bc87:7b6c:fb2a]) by smtp.googlemail.com with ESMTPSA id w5-20020a7bc105000000b0038eb9932dacsm5230980wmi.48.2022.04.15.09.55.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Apr 2022 09:55:20 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <53ddaaed-3d98-2153-3d28-c865ad695253@redhat.com> Date: Fri, 15 Apr 2022 18:55:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [RFC PATCH v5 019/104] KVM: TDX: Stub in tdx.h with structs, accessors, and VMCS helpers Content-Language: en-US To: isaku.yamahata@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@gmail.com, Jim Mattson , erdemaktas@google.com, Connor Kuehl , Sean Christopherson References: From: Paolo Bonzini In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 3/4/22 20:48, isaku.yamahata@intel.com wrote: > From: Sean Christopherson > > Stub in kvm_tdx, vcpu_tdx, and their various accessors. TDX defines > SEAMCALL APIs to access TDX control structures corresponding to the VMX > VMCS. Introduce helper accessors to hide its SEAMCALL ABI details. > > Signed-off-by: Sean Christopherson > Signed-off-by: Isaku Yamahata > --- > arch/x86/kvm/vmx/tdx.h | 101 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 101 insertions(+) When rebasing against tip/x86/tdx, the new .h file needs to include asm/tdx.h. Paolo > diff --git a/arch/x86/kvm/vmx/tdx.h b/arch/x86/kvm/vmx/tdx.h > index 616fbf79b129..e4bb8831764e 100644 > --- a/arch/x86/kvm/vmx/tdx.h > +++ b/arch/x86/kvm/vmx/tdx.h > @@ -3,14 +3,29 @@ > #define __KVM_X86_TDX_H > > #ifdef CONFIG_INTEL_TDX_HOST > + > +#include "tdx_ops.h" > + > int tdx_module_setup(void); > > +struct tdx_td_page { > + unsigned long va; > + hpa_t pa; > + bool added; > +}; > + > struct kvm_tdx { > struct kvm kvm; > + > + struct tdx_td_page tdr; > + struct tdx_td_page *tdcs; > }; > > struct vcpu_tdx { > struct kvm_vcpu vcpu; > + > + struct tdx_td_page tdvpr; > + struct tdx_td_page *tdvpx; > }; > > static inline bool is_td(struct kvm *kvm) > @@ -32,6 +47,92 @@ static inline struct vcpu_tdx *to_tdx(struct kvm_vcpu *vcpu) > { > return container_of(vcpu, struct vcpu_tdx, vcpu); > } > + > +static __always_inline void tdvps_vmcs_check(u32 field, u8 bits) > +{ > + BUILD_BUG_ON_MSG(__builtin_constant_p(field) && (field) & 0x1, > + "Read/Write to TD VMCS *_HIGH fields not supported"); > + > + BUILD_BUG_ON(bits != 16 && bits != 32 && bits != 64); > + > + BUILD_BUG_ON_MSG(bits != 64 && __builtin_constant_p(field) && > + (((field) & 0x6000) == 0x2000 || > + ((field) & 0x6000) == 0x6000), > + "Invalid TD VMCS access for 64-bit field"); > + BUILD_BUG_ON_MSG(bits != 32 && __builtin_constant_p(field) && > + ((field) & 0x6000) == 0x4000, > + "Invalid TD VMCS access for 32-bit field"); > + BUILD_BUG_ON_MSG(bits != 16 && __builtin_constant_p(field) && > + ((field) & 0x6000) == 0x0000, > + "Invalid TD VMCS access for 16-bit field"); > +} > + > +static __always_inline void tdvps_state_non_arch_check(u64 field, u8 bits) {} > +static __always_inline void tdvps_management_check(u64 field, u8 bits) {} > + > +#define TDX_BUILD_TDVPS_ACCESSORS(bits, uclass, lclass) \ > +static __always_inline u##bits td_##lclass##_read##bits(struct vcpu_tdx *tdx, \ > + u32 field) \ > +{ \ > + struct tdx_module_output out; \ > + u64 err; \ > + \ > + tdvps_##lclass##_check(field, bits); \ > + err = tdh_vp_rd(tdx->tdvpr.pa, TDVPS_##uclass(field), &out); \ > + if (unlikely(err)) { \ > + pr_err("TDH_VP_RD["#uclass".0x%x] failed: 0x%llx\n", \ > + field, err); \ > + return 0; \ > + } \ > + return (u##bits)out.r8; \ > +} \ > +static __always_inline void td_##lclass##_write##bits(struct vcpu_tdx *tdx, \ > + u32 field, u##bits val) \ > +{ \ > + struct tdx_module_output out; \ > + u64 err; \ > + \ > + tdvps_##lclass##_check(field, bits); \ > + err = tdh_vp_wr(tdx->tdvpr.pa, TDVPS_##uclass(field), val, \ > + GENMASK_ULL(bits - 1, 0), &out); \ > + if (unlikely(err)) \ > + pr_err("TDH_VP_WR["#uclass".0x%x] = 0x%llx failed: 0x%llx\n", \ > + field, (u64)val, err); \ > +} \ > +static __always_inline void td_##lclass##_setbit##bits(struct vcpu_tdx *tdx, \ > + u32 field, u64 bit) \ > +{ \ > + struct tdx_module_output out; \ > + u64 err; \ > + \ > + tdvps_##lclass##_check(field, bits); \ > + err = tdh_vp_wr(tdx->tdvpr.pa, TDVPS_##uclass(field), bit, bit, \ > + &out); \ > + if (unlikely(err)) \ > + pr_err("TDH_VP_WR["#uclass".0x%x] |= 0x%llx failed: 0x%llx\n", \ > + field, bit, err); \ > +} \ > +static __always_inline void td_##lclass##_clearbit##bits(struct vcpu_tdx *tdx, \ > + u32 field, u64 bit) \ > +{ \ > + struct tdx_module_output out; \ > + u64 err; \ > + \ > + tdvps_##lclass##_check(field, bits); \ > + err = tdh_vp_wr(tdx->tdvpr.pa, TDVPS_##uclass(field), 0, bit, \ > + &out); \ > + if (unlikely(err)) \ > + pr_err("TDH_VP_WR["#uclass".0x%x] &= ~0x%llx failed: 0x%llx\n", \ > + field, bit, err); \ > +} > + > +TDX_BUILD_TDVPS_ACCESSORS(16, VMCS, vmcs); > +TDX_BUILD_TDVPS_ACCESSORS(32, VMCS, vmcs); > +TDX_BUILD_TDVPS_ACCESSORS(64, VMCS, vmcs); > + > +TDX_BUILD_TDVPS_ACCESSORS(64, STATE_NON_ARCH, state_non_arch); > +TDX_BUILD_TDVPS_ACCESSORS(8, MANAGEMENT, management); > + > #else > static inline int tdx_module_setup(void) { return -ENODEV; }; >