Re: [PATCH v2] target/ppc: Generate storage interrupts for radix RC changes

[Daniel Henrique Barboza <danielhb413@gmail.com>]

On 7/20/23 23:38, Nicholas Piggin wrote:
> On Thu Jul 13, 2023 at 3:35 AM AEST, Shawn Anastasio wrote:
>> On 7/12/23 11:56 AM, Cédric Le Goater wrote:
>>> Hello Shawn,
>>>
>>> On 7/12/23 18:13, Shawn Anastasio wrote:
>>>> Change radix model to always generate a storage interrupt when the R/C
>>>> bits are not set appropriately in a PTE instead of setting the bits
>>>> itself.  According to the ISA both behaviors are valid, but in practice
>>>> this change more closely matches behavior observed on the POWER9 CPU.
>>>
>>> How did you spotted this dark corner case in emulation ? Do you have
>>> MMU unit tests ?
>>
>> I'm currently porting Xen to Power and have been using QEMU's powernv
>> model extensively for early bring up. I noticed the issue when my radix
>> implementation worked in QEMU but failed on actual hardware since I
>> didn't have a proper storage interrupt handler implemented.
> 
> Cool. This was on my todo list because we rely on it for nested HV
> KVM too.
> 
> I actually didn't know about that odd effLIPD=0 exception, but it
> looks right. How did you test that, by running with MSR[HV]=0 and
> LPIDR=0 ?
> 
> For the patch,
> 
> Reviewed-by: Nicholas Piggin <npiggin@gmail.com>

Cedric, do you think this is 8.1 material?


Daniel

> 
> Thanks,
> Nick