From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86F1EC25B67 for ; Fri, 27 Oct 2023 09:24:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oobv7ZMAEVovj7m/8QIjr0Yx2+AvUhIAilQMzSEGaBs=; b=0cnu6zn+T4ClmF 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Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 27 Oct 2023 17:23:50 +0800 Received: from [192.168.125.131] (183.27.99.126) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 27 Oct 2023 17:23:49 +0800 Message-ID: <540136d4-6f8f-49a6-80ff-cc621f2f462b@starfivetech.com> Date: Fri, 27 Oct 2023 17:17:30 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/3] clocksource: Add JH7110 timer driver Content-Language: en-US To: Daniel Lezcano , Thomas Gleixner , Emil Renner Berthing , Christophe JAILLET CC: , , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Walker Chen , Samin Guo , , Conor Dooley References: <20231019053501.46899-1-xingyu.wu@starfivetech.com> <20231019053501.46899-3-xingyu.wu@starfivetech.com> <3f76f965-7c7b-109e-2ee0-3033e332e84b@linaro.org> From: Xingyu Wu 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IHRpbWVyIGRyaXZlciBmb3IgdGhlIFN0YXJGaXZlIEpINzExMCBTb0MuCj4+Pgo+Pj4gQXMgaXQg aXMgYSBuZXcgdGltZXIsIHBsZWFzZSBhZGQgYSBwcm9wZXIgbmljZSBkZXNjcmlwdGlvbiBleHBs YWluaW5nIHRoZSB0aW1lciBoYXJkd2FyZSwgdGhhbmtzLgo+Pgo+PiBPSy4gV2lsbCBhZGQgdGhl IGRlc2NyaXB0aW9uIGluIG5leHQgdmVyc2lvbi4KPj4KPj4+Cj4+Pj4gU2lnbmVkLW9mZi1ieTog WGluZ3l1IFd1IDx4aW5neXUud3VAc3RhcmZpdmV0ZWNoLmNvbT4KPj4+PiAtLS0KPj4+PiDCoMKg IE1BSU5UQUlORVJTwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oCB8wqDCoCA3ICsKPj4+PiDCoMKgIGRyaXZlcnMvY2xvY2tzb3VyY2UvS2NvbmZpZ8KgwqDCoMKg wqDCoMKgIHzCoCAxMSArCj4+Pj4gwqDCoCBkcml2ZXJzL2Nsb2Nrc291cmNlL01ha2VmaWxlwqDC oMKgwqDCoMKgIHzCoMKgIDEgKwo+Pj4+IMKgwqAgZHJpdmVycy9jbG9ja3NvdXJjZS90aW1lci1q aDcxMTAuYyB8IDM4MCArKysrKysrKysrKysrKysrKysrKysrKysrKysrKwo+Pj4+IMKgwqAgNCBm aWxlcyBjaGFuZ2VkLCAzOTkgaW5zZXJ0aW9ucygrKQo+Pj4+IMKgwqAgY3JlYXRlIG1vZGUgMTAw NjQ0IGRyaXZlcnMvY2xvY2tzb3VyY2UvdGltZXItamg3MTEwLmMKPj4+Pgo+Pj4+IGRpZmYgLS1n aXQgYS9NQUlOVEFJTkVSUyBiL01BSU5UQUlORVJTCj4+Pj4gaW5kZXggN2E3YmQ4YmQ4MGU5Li45 MWMwOWIzOTkxMzEgMTAwNjQ0Cj4+Pj4gLS0tIGEvTUFJTlRBSU5FUlMKPj4+PiArKysgYi9NQUlO VEFJTkVSUwo+Pj4+IEBAIC0yMDQ3Myw2ICsyMDQ3MywxMyBAQCBTOsKgwqDCoCBNYWludGFpbmVk Cj4+Pj4gwqDCoCBGOsKgwqDCoCBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3Mvc291 bmQvc3RhcmZpdmUsamg3MTEwLXRkbS55YW1sCj4+Pj4gwqDCoCBGOsKgwqDCoCBzb3VuZC9zb2Mv c3RhcmZpdmUvamg3MTEwX3RkbS5jCj4+Pj4gwqDCoCArU1RBUkZJVkUgSkg3MTEwIFRJTUVSIERS SVZFUgo+Pj4+ICtNOsKgwqDCoCBTYW1pbiBHdW8gPHNhbWluLmd1b0BzdGFyZml2ZXRlY2guY29t Pgo+Pj4+ICtNOsKgwqDCoCBYaW5neXUgV3UgPHhpbmd5dS53dUBzdGFyZml2ZXRlY2guY29tPgo+ Pj4+ICtTOsKgwqDCoCBTdXBwb3J0ZWQKPj4+PiArRjrCoMKgwqAgRG9jdW1lbnRhdGlvbi9kZXZp Y2V0cmVlL2JpbmRpbmdzL3RpbWVyL3N0YXJmaXZlLGpoNzExMC10aW1lci55YW1sCj4+Pj4gK0Y6 wqDCoMKgIGRyaXZlcnMvY2xvY2tzb3VyY2UvdGltZXItamg3MTEwLmMKPj4+PiArCj4+Pj4gwqDC oCBTVEFSRklWRSBKSDcxWDAgQ0xPQ0sgRFJJVkVSUwo+Pj4+IMKgwqAgTTrCoMKgwqAgRW1pbCBS ZW5uZXIgQmVydGhpbmcgPGtlcm5lbEBlc21pbC5kaz4KPj4+PiDCoMKgIE06wqDCoMKgIEhhbCBG ZW5nIDxoYWwuZmVuZ0BzdGFyZml2ZXRlY2guY29tPgo+Pj4+IGRpZmYgLS1naXQgYS9kcml2ZXJz L2Nsb2Nrc291cmNlL0tjb25maWcgYi9kcml2ZXJzL2Nsb2Nrc291cmNlL0tjb25maWcKPj4+PiBp bmRleCAwYmEwZGM0ZWNmMDYuLjgyMWFiY2MxZTUxNyAxMDA2NDQKPj4+PiAtLS0gYS9kcml2ZXJz L2Nsb2Nrc291cmNlL0tjb25maWcKPj4+PiArKysgYi9kcml2ZXJzL2Nsb2Nrc291cmNlL0tjb25m aWcKPj4+PiBAQCAtNjQxLDYgKzY0MSwxNyBAQCBjb25maWcgUklTQ1ZfVElNRVIKPj4+PiDCoMKg wqDCoMKgwqDCoMKgIGlzIGFjY2Vzc2VkIHZpYSBib3RoIHRoZSBTQkkgYW5kIHRoZSByZGN5Y2xl IGluc3RydWN0aW9uLsKgIFRoaXMgaXMKPj4+PiDCoMKgwqDCoMKgwqDCoMKgIHJlcXVpcmVkIGZv ciBhbGwgUklTQy1WIHN5c3RlbXMuCj4+Pj4gwqDCoCArY29uZmlnIFNUQVJGSVZFX0pINzExMF9U SU1FUgo+Pj4+ICvCoMKgwqAgYm9vbCAiVGltZXIgZm9yIHRoZSBTVEFSRklWRSBKSDcxMTAgU29D Igo+Pj4+ICvCoMKgwqAgZGVwZW5kcyBvbiBBUkNIX1NUQVJGSVZFIHx8IENPTVBJTEVfVEVTVAo+ Pj4KPj4+IFlvdSBtYXkgd2FudCB0byB1c2UgQVJDSF9TVEFSRklWRSBvbmx5IGlmIHRoZSBwbGF0 Zm9ybSBjYW4gbWFrZSB0aGlzIHRpbWVyIG9wdGlvbmFsLiBPdGhlcndpc2UsIHNldCB0aGUgb3B0 aW9uIGZyb20gdGhlIHBsYXRmb3JtIEtjb25maWcgYW5kIHB1dCB0aGUgYm9vbCAiYmxhIGJsYSIg aWYgQ09NUElMRV9URVNUCj4+Cj4+IFllcywgdGhpcyB0aW1lciBvbmx5IGJlIHVzZWQgb24gdGhl IFN0YXJGaXZlIFNvQy4gU28gSSBpbnRlbmQgdG8gbW9kaWZ5IHRvIHRoaXM6Cj4+Cj4+IGJvb2wg IlRpbWVyIGZvciB0aGUgU1RBUkZJVkUgSkg3MTEwIFNvQyIgaWYgQ09NUElMRV9URVNUCj4+IGRl cGVuZHMgb24gQVJDSF9TVEFSRklWRQo+IAo+IEluIHRoaXMgY2FzZSwgeW91IHNob3VsZCBjaGFu Z2UgdGhlIHBsYXRmb3JtIGNvbmZpZyBhbmQgc2VsZWN0IHRoZSB0aW1lciBmcm9tIHRoZXJlLiBS ZW1vdmUgdGhlIGRlcGVuZHMgb24gQVJDSF9TVEFSRklWRSBzbyBpdCBpcyBwb3NzaWJsZSBlbmFi bGUgY3Jvc3MgdGVzdCBjb21waWxhdGlvbi4gT3RoZXJ3aXNlIENPTVBJTEVfVEVTVCB3aWxsIG5v dCB3b3JrIG9uIG90aGVyIHBsYXRmb3Jtcy4KPiAKPiBbIC4uLiBdCj4gCgpJdCBpcyBub3QgYSBr ZXJuZWwgdGltZXIgb3IgY2xvY2tzb3VyY2UuIEl0IHdpbGwgbm90IHdvcmsgb24gb3RoZXIgcGxh dGZvcm1zIGFuZCBpcyBqdXN0IHVzZWQgb24gdGhlIEpINzExMCBTb0MuCkkgdGhpbmsgSSBuZWVk bid0IHJlbW92ZSBpdC4gTWF5YmUgSSBtb2RpZnkgdG8gdGhpczoKCmJvb2wgIlRpbWVyIGZvciB0 aGUgU1RBUkZJVkUgSkg3MTEwIFNvQyIgaWYgQ09NUElMRV9URVNUCmRlcGVuZHMgb24gQVJDSF9T VEFSRklWRSB8fCBDT01QSUxFX1RFU1QKCj4+Pj4gK3N0cnVjdCBqaDcxMTBfY2xrZXZ0IHsKPj4+ PiArwqDCoMKgIHN0cnVjdCBjbG9ja19ldmVudF9kZXZpY2UgZXZ0Owo+Pj4+ICvCoMKgwqAgc3Ry dWN0IGNsb2Nrc291cmNlIGNzOwo+Pj4+ICvCoMKgwqAgYm9vbCBjc19pc192YWxpZDsKPj4+PiAr wqDCoMKgIHN0cnVjdCBjbGsgKmNsazsKPj4+PiArwqDCoMKgIHN0cnVjdCByZXNldF9jb250cm9s ICpyc3Q7Cj4+Pj4gK8KgwqDCoCB1MzIgcmF0ZTsKPj4+PiArwqDCoMKgIHUzMiByZWxvYWRfdmFs Owo+Pj4+ICvCoMKgwqAgdm9pZCBfX2lvbWVtICpiYXNlOwo+Pj4+ICvCoMKgwqAgY2hhciBuYW1l W3NpemVvZigiamg3MTEwLXRpbWVyLmNoWCIpXTsKPj4+PiArfTsKPj4+PiArCj4+Pj4gK3N0cnVj dCBqaDcxMTBfdGltZXJfcHJpdiB7Cj4+Pj4gK8KgwqDCoCBzdHJ1Y3QgY2xrICpwY2xrOwo+Pj4+ ICvCoMKgwqAgc3RydWN0IHJlc2V0X2NvbnRyb2wgKnByc3Q7Cj4+Pj4gK8KgwqDCoCBzdHJ1Y3Qg amg3MTEwX2Nsa2V2dCBjbGtldnRbSkg3MTEwX1RJTUVSX0NIX01BWF07Cj4+Pgo+Pj4gV2h5IGRv IHlvdSBuZWVkIHNldmVyYWwgY2xvY2sgZXZlbnRzIGFuZCBjbG9jayBzb3VyY2VzID8KPj4KPj4g VGhpcyB0aW1lciBoYXMgZm91ciBjb3VudGVycyAoY2hhbm5lbHMpIHdoaWNoIHJ1biBpbmRlcGVu ZGVudGx5LiBTbyBlYWNoIGNvdW50ZXIgY2FuIGhhdmUgaXRzIG93biBjbG9jayBldmVudCBhbmQg Y2xvY2sgc291cmNlIHRvIGNvbmZpZ3VyZSBkaWZmZXJlbnQgc2V0dGluZ3MuCj4gCj4gVGhlIGtl cm5lbCBvbmx5IG5lZWRzIG9uZSBjbG9ja3NvdXJjZS4gVXN1YWxseSBtdWx0aXBsZSBjbG9ja2V2 ZW50cyBhcmUgcGVyLWNwdSBiYXNlZCBzeXN0ZW0uCj4gCj4gVGhlIGRyaXZlciBkb2VzIG5vdCBz ZWVtIHRvIGhhdmUgYSBwZXIgY3B1IHRpbWVyIGJ1dCBqdXN0IGluaXRpYWxpemluZyBtdWx0aXBs ZSBjbG9ja2V2ZW50cyB3aGljaCB3aWxsIGVuZCB1cCB1bnVzZWQsIHdhc3RpbmcgZW5lcmd5Lgo+ IAo+IAoKVGhlIGJvYXJkIG9mIHRoZSBTdGFyRml2ZSBKSDcxMTAgU29DIGhhcyB0d28gdHlwZXMg b2YgdGltZXIgOiByaXNjdi10aW1lciBhbmQgamg3MTEwLXRpbWVyLiBJdCBib290cyBieSByaXNj di10aW1lcihjbG9ja3NvdXJjZSkgYW5kIHRoZSBqaDcxMTAtdGltZXIgaXMgb3B0aW9uYWwgYW5k IGFkZGl0aW9uYWwuCkkgdGhpbmsgSSBzaG91bGQgaW5pdGlhbGl6ZSB0aGUgZm91ciBjaGFubmVs cyBvZiBqaDcxMTAtdGltZXIgYXMgY2xvY2tldmVudHMgbm90IGNsb2Nrc291cmNlIHByZS1jcHUu CgpUaGFua3MsClhpbmd5dSBXdQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX18KbGludXgtcmlzY3YgbWFpbGluZyBsaXN0CmxpbnV4LXJpc2N2QGxpc3RzLmlu ZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9s aW51eC1yaXNjdgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C39F58C0C for ; Fri, 27 Oct 2023 09:23:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B6621A5; Fri, 27 Oct 2023 02:23:53 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 4ABE824E1F0; Fri, 27 Oct 2023 17:23:50 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 27 Oct 2023 17:23:50 +0800 Received: from [192.168.125.131] (183.27.99.126) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 27 Oct 2023 17:23:49 +0800 Message-ID: <540136d4-6f8f-49a6-80ff-cc621f2f462b@starfivetech.com> Date: Fri, 27 Oct 2023 17:17:30 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/3] clocksource: Add JH7110 timer driver Content-Language: en-US To: Daniel Lezcano , Thomas Gleixner , Emil Renner Berthing , Christophe JAILLET CC: , , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Walker Chen , Samin Guo , , Conor Dooley References: <20231019053501.46899-1-xingyu.wu@starfivetech.com> <20231019053501.46899-3-xingyu.wu@starfivetech.com> <3f76f965-7c7b-109e-2ee0-3033e332e84b@linaro.org> From: Xingyu Wu In-Reply-To: Content-Type: text/plain; charset="UTF-8" X-Originating-IP: [183.27.99.126] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable On 2023/10/25 22:39, Daniel Lezcano wrote: >=20 > Hi Xingyu, >=20 >=20 > On 25/10/2023 11:04, Xingyu Wu wrote: >> On 2023/10/24 22:56, Daniel Lezcano wrote: >>> >>> Hi Xingyu, >>> >>> >>> On 19/10/2023 07:35, Xingyu Wu wrote: >>>> Add timer driver for the StarFive JH7110 SoC. >>> >>> As it is a new timer, please add a proper nice description explaining= the timer hardware, thanks. >> >> OK. Will add the description in next version. >> >>> >>>> Signed-off-by: Xingyu Wu >>>> --- >>>> =C2=A0=C2=A0 MAINTAINERS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 7 + >>>> =C2=A0=C2=A0 drivers/clocksource/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 |=C2=A0 11 + >>>> =C2=A0=C2=A0 drivers/clocksource/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0=C2=A0 1 + >>>> =C2=A0=C2=A0 drivers/clocksource/timer-jh7110.c | 380 ++++++++++++++= +++++++++++++++ >>>> =C2=A0=C2=A0 4 files changed, 399 insertions(+) >>>> =C2=A0=C2=A0 create mode 100644 drivers/clocksource/timer-jh7110.c >>>> >>>> diff --git a/MAINTAINERS b/MAINTAINERS >>>> index 7a7bd8bd80e9..91c09b399131 100644 >>>> --- a/MAINTAINERS >>>> +++ b/MAINTAINERS >>>> @@ -20473,6 +20473,13 @@ S:=C2=A0=C2=A0=C2=A0 Maintained >>>> =C2=A0=C2=A0 F:=C2=A0=C2=A0=C2=A0 Documentation/devicetree/bindings/= sound/starfive,jh7110-tdm.yaml >>>> =C2=A0=C2=A0 F:=C2=A0=C2=A0=C2=A0 sound/soc/starfive/jh7110_tdm.c >>>> =C2=A0=C2=A0 +STARFIVE JH7110 TIMER DRIVER >>>> +M:=C2=A0=C2=A0=C2=A0 Samin Guo >>>> +M:=C2=A0=C2=A0=C2=A0 Xingyu Wu >>>> +S:=C2=A0=C2=A0=C2=A0 Supported >>>> +F:=C2=A0=C2=A0=C2=A0 Documentation/devicetree/bindings/timer/starfi= ve,jh7110-timer.yaml >>>> +F:=C2=A0=C2=A0=C2=A0 drivers/clocksource/timer-jh7110.c >>>> + >>>> =C2=A0=C2=A0 STARFIVE JH71X0 CLOCK DRIVERS >>>> =C2=A0=C2=A0 M:=C2=A0=C2=A0=C2=A0 Emil Renner Berthing >>>> =C2=A0=C2=A0 M:=C2=A0=C2=A0=C2=A0 Hal Feng >>>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconf= ig >>>> index 0ba0dc4ecf06..821abcc1e517 100644 >>>> --- a/drivers/clocksource/Kconfig >>>> +++ b/drivers/clocksource/Kconfig >>>> @@ -641,6 +641,17 @@ config RISCV_TIMER >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 is accessed via bot= h the SBI and the rdcycle instruction.=C2=A0 This is >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 required for all RI= SC-V systems. >>>> =C2=A0=C2=A0 +config STARFIVE_JH7110_TIMER >>>> +=C2=A0=C2=A0=C2=A0 bool "Timer for the STARFIVE JH7110 SoC" >>>> +=C2=A0=C2=A0=C2=A0 depends on ARCH_STARFIVE || COMPILE_TEST >>> >>> You may want to use ARCH_STARFIVE only if the platform can make this = timer optional. Otherwise, set the option from the platform Kconfig and p= ut the bool "bla bla" if COMPILE_TEST >> >> Yes, this timer only be used on the StarFive SoC. So I intend to modif= y to this: >> >> bool "Timer for the STARFIVE JH7110 SoC" if COMPILE_TEST >> depends on ARCH_STARFIVE >=20 > In this case, you should change the platform config and select the time= r from there. Remove the depends on ARCH_STARFIVE so it is possible enabl= e cross test compilation. Otherwise COMPILE_TEST will not work on other p= latforms. >=20 > [ ... ] >=20 It is not a kernel timer or clocksource. It will not work on other platfo= rms and is just used on the JH7110 SoC. I think I needn't remove it. Maybe I modify to this: bool "Timer for the STARFIVE JH7110 SoC" if COMPILE_TEST depends on ARCH_STARFIVE || COMPILE_TEST >>>> +struct jh7110_clkevt { >>>> +=C2=A0=C2=A0=C2=A0 struct clock_event_device evt; >>>> +=C2=A0=C2=A0=C2=A0 struct clocksource cs; >>>> +=C2=A0=C2=A0=C2=A0 bool cs_is_valid; >>>> +=C2=A0=C2=A0=C2=A0 struct clk *clk; >>>> +=C2=A0=C2=A0=C2=A0 struct reset_control *rst; >>>> +=C2=A0=C2=A0=C2=A0 u32 rate; >>>> +=C2=A0=C2=A0=C2=A0 u32 reload_val; >>>> +=C2=A0=C2=A0=C2=A0 void __iomem *base; >>>> +=C2=A0=C2=A0=C2=A0 char name[sizeof("jh7110-timer.chX")]; >>>> +}; >>>> + >>>> +struct jh7110_timer_priv { >>>> +=C2=A0=C2=A0=C2=A0 struct clk *pclk; >>>> +=C2=A0=C2=A0=C2=A0 struct reset_control *prst; >>>> +=C2=A0=C2=A0=C2=A0 struct jh7110_clkevt clkevt[JH7110_TIMER_CH_MAX]= ; >>> >>> Why do you need several clock events and clock sources ? >> >> This timer has four counters (channels) which run independently. So ea= ch counter can have its own clock event and clock source to configure dif= ferent settings. >=20 > The kernel only needs one clocksource. Usually multiple clockevents are= per-cpu based system. >=20 > The driver does not seem to have a per cpu timer but just initializing = multiple clockevents which will end up unused, wasting energy. >=20 >=20 The board of the StarFive JH7110 SoC has two types of timer : riscv-timer= and jh7110-timer. It boots by riscv-timer(clocksource) and the jh7110-ti= mer is optional and additional. I think I should initialize the four channels of jh7110-timer as clockeve= nts not clocksource pre-cpu. Thanks, Xingyu Wu