From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH] x86: remove redundancy of MSR_P6_{PERFCTR,
 EVNTSEL} definitions
Date: Wed, 3 Sep 2014 13:30:53 +0100
Message-ID: <540709FD.7090904@citrix.com>
References: <5407252E0200007800030433@mail.emea.novell.com>
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To: Jan Beulich <JBeulich@suse.com>, xen-devel <xen-devel@lists.xenproject.org>
Cc: Eddie Dong <eddie.dong@intel.com>, Kevin Tian <kevin.tian@intel.com>, Keir Fraser <keir@xen.org>, Jun Nakajima <jun.nakajima@intel.com>
List-Id: xen-devel@lists.xenproject.org

On 03/09/14 13:26, Jan Beulich wrote:
> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -112,11 +112,6 @@
>  
>  #define MSR_AMD64_MCx_MASK(x)		(MSR_AMD64_MC0_MASK + (x))
>  
> -#define MSR_P6_PERFCTR0			0x000000c1
> -#define MSR_P6_PERFCTR1			0x000000c2
> -#define MSR_P6_EVNTSEL0			0x00000186
> -#define MSR_P6_EVNTSEL1			0x00000187
> -
>  /* MSRs & bits used for VMX enabling */
>  #define MSR_IA32_VMX_BASIC                      0x480
>  #define MSR_IA32_VMX_PINBASED_CTLS              0x481
> @@ -329,8 +324,8 @@
>  #define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0
>  
>  /* Intel Model 6 */
> -#define MSR_P6_EVNTSEL0			0x00000186
> -#define MSR_P6_EVNTSEL1			0x00000187
> +#define MSR_P6_PERFCTR(n)		(0x000000c1 + (n))
> +#define MSR_P6_EVNTSEL(n)		(0x00000186 + (n))
>  
>  /* P4/Xeon+ specific */
>  #define MSR_IA32_MCG_EAX		0x00000180
> @@ -488,7 +483,4 @@
>  #define _MSR_MISC_FEATURES_CPUID_FAULTING	0
>  #define MSR_MISC_FEATURES_CPUID_FAULTING	(1ULL << _MSR_MISC_FEATURES_CPUID_FAULTING)
>  
> -/* Geode defined MSRs */
> -#define MSR_GEODE_BUSCONT_CONF0		0x00001900
> -

Is this geode removal related to the patch?

Other than this hunk, Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

~Andrew