Re: [Qemu-devel] [PATCH 08/17] ppc: introduce helpers for mfocrf/mtocrf

[Tom Musta <tommusta@gmail.com>]

On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  target-ppc/helper.h     |  3 +++
>  target-ppc/int_helper.c | 22 ++++++++++++++++++++++
>  target-ppc/translate.c  | 31 ++++---------------------------
>  3 files changed, 29 insertions(+), 27 deletions(-)
> 
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 509eae5..5342f13 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -60,6 +60,9 @@ DEF_HELPER_2(fpscr_setbit, void, env, i32)
>  DEF_HELPER_2(float64_to_float32, i32, env, i64)
>  DEF_HELPER_2(float32_to_float64, i64, env, i32)
>  
> +DEF_HELPER_1(mfocrf, tl, env)
> +DEF_HELPER_3(mtocrf, void, env, tl, i32)
> +
>  DEF_HELPER_4(fcmpo, void, env, i64, i64, i32)
>  DEF_HELPER_4(fcmpu, void, env, i64, i64, i32)
>  
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 7955bf7..5fa10c7 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -306,6 +306,28 @@ target_ulong helper_popcntw(target_ulong val)
>  }
>  #endif
>  
> +void helper_mtocrf(CPUPPCState *env, target_ulong cr, uint32_t mask)
> +{
> +    int i;
> +    for (i = 7; i >= 0; i--) {
> +        if (mask & 1) {
> +            env->crf[i] = cr & 0x0F;
> +        }
> +        cr >>= 4;
> +        mask >>= 1;
> +    }
> +}

Use ARRAY_SIZE?

> +
> +target_ulong helper_mfocrf(CPUPPCState *env)
> +{
> +    uint32_t cr = 0;
> +    int i;
> +    for (i = 0; i < 8; i++) {
> +        cr |= env->crf[i] << (32 - (i + 1) * 4);
> +    }
> +    return cr;
> +}
> +

Use ARRAY_SIZE?  Or better yet, reuse the utility that I recommended adding as part of patch 4.

>  /*****************************************************************************/
>  /* PowerPC 601 specific instructions (POWER bridge) */
>  target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 5a8267a..0a85a23 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -4145,24 +4145,7 @@ static void gen_mfcr(DisasContext *ctx)
>                              cpu_gpr[rD(ctx->opcode)], crn * 4);
>          }
>      } else {
> -        TCGv_i32 t0 = tcg_temp_new_i32();
> -        tcg_gen_mov_i32(t0, cpu_crf[0]);
> -        tcg_gen_shli_i32(t0, t0, 4);
> -        tcg_gen_or_i32(t0, t0, cpu_crf[1]);
> -        tcg_gen_shli_i32(t0, t0, 4);
> -        tcg_gen_or_i32(t0, t0, cpu_crf[2]);
> -        tcg_gen_shli_i32(t0, t0, 4);
> -        tcg_gen_or_i32(t0, t0, cpu_crf[3]);
> -        tcg_gen_shli_i32(t0, t0, 4);
> -        tcg_gen_or_i32(t0, t0, cpu_crf[4]);
> -        tcg_gen_shli_i32(t0, t0, 4);
> -        tcg_gen_or_i32(t0, t0, cpu_crf[5]);
> -        tcg_gen_shli_i32(t0, t0, 4);
> -        tcg_gen_or_i32(t0, t0, cpu_crf[6]);
> -        tcg_gen_shli_i32(t0, t0, 4);
> -        tcg_gen_or_i32(t0, t0, cpu_crf[7]);
> -        tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
> -        tcg_temp_free_i32(t0);
> +        gen_helper_mfocrf(cpu_gpr[rD(ctx->opcode)], cpu_env);
>      }
>  }
>  
> @@ -4257,15 +4240,9 @@ static void gen_mtcrf(DisasContext *ctx)
>              tcg_temp_free_i32(temp);
>          }
>      } else {
> -        TCGv_i32 temp = tcg_temp_new_i32();
> -        tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
> -        for (crn = 0 ; crn < 8 ; crn++) {
> -            if (crm & (1 << crn)) {
> -                    tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
> -                    tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
> -            }
> -        }
> -        tcg_temp_free_i32(temp);
> +        TCGv_i32 t0 = tcg_const_i32(crm);
> +        gen_helper_mtocrf(cpu_env, cpu_gpr[rS(ctx->opcode)], t0);
> +        tcg_temp_free_i32(t0);
>      }
>  }
>  
>