From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59995) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XPnw3-0006uQ-MS for qemu-devel@nongnu.org; Fri, 05 Sep 2014 03:28:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XPnvw-0005Ke-54 for qemu-devel@nongnu.org; Fri, 05 Sep 2014 03:27:55 -0400 Message-ID: <540965F3.2040705@suse.de> Date: Fri, 05 Sep 2014 09:27:47 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1409246113-6519-1-git-send-email-pbonzini@redhat.com> <1409246113-6519-12-git-send-email-pbonzini@redhat.com> <54076EDE.3050208@gmail.com> In-Reply-To: <54076EDE.3050208@gmail.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 11/17] ppc: rename gen_set_cr6_from_fpscr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , Paolo Bonzini , qemu-devel@nongnu.org Cc: dgibson@redhat.com, qemu-ppc@nongnu.org On 03.09.14 21:41, Tom Musta wrote: > On 8/28/2014 12:15 PM, Paolo Bonzini wrote: >> It sets CR1, not CR6 (and the spec agrees). >> >> Signed-off-by: Paolo Bonzini >> --- >> target-ppc/translate.c | 14 +++++++------- >> 1 file changed, 7 insertions(+), 7 deletions(-) >> >> diff --git a/target-ppc/translate.c b/target-ppc/translate.c >> index 8def0ae..67f13f7 100644 >> --- a/target-ppc/translate.c >> +++ b/target-ppc/translate.c >> @@ -8179,7 +8179,7 @@ static inline TCGv_ptr gen_fprp_ptr(int reg) >> } >> >> #if defined(TARGET_PPC64) >> -static void gen_set_cr6_from_fpscr(DisasContext *ctx) >> +static void gen_set_cr1_from_fpscr(DisasContext *ctx) >> { >> TCGv_i32 tmp = tcg_temp_new_i32(); >> tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); >> @@ -8187,7 +8187,7 @@ static void gen_set_cr6_from_fpscr(DisasContext *ctx) >> tcg_temp_free_i32(tmp); >> } >> #else >> -static void gen_set_cr6_from_fpscr(DisasContext *ctx) >> +static void gen_set_cr1_from_fpscr(DisasContext *ctx) >> { >> gen_op_mtcr(4, cpu_fpscr, 28); >> } >> @@ -8207,7 +8207,7 @@ static void gen_##name(DisasContext *ctx) \ >> rb = gen_fprp_ptr(rB(ctx->opcode)); \ >> gen_helper_##name(cpu_env, rd, ra, rb); \ >> if (unlikely(Rc(ctx->opcode) != 0)) { \ >> - gen_set_cr6_from_fpscr(ctx); \ >> + gen_set_cr1_from_fpscr(ctx); \ >> } \ >> tcg_temp_free_ptr(rd); \ >> tcg_temp_free_ptr(ra); \ >> @@ -8265,7 +8265,7 @@ static void gen_##name(DisasContext *ctx) \ >> u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \ >> gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \ >> if (unlikely(Rc(ctx->opcode) != 0)) { \ >> - gen_set_cr6_from_fpscr(ctx); \ >> + gen_set_cr1_from_fpscr(ctx); \ >> } \ >> tcg_temp_free_ptr(rt); \ >> tcg_temp_free_ptr(rb); \ >> @@ -8289,7 +8289,7 @@ static void gen_##name(DisasContext *ctx) \ >> i32 = tcg_const_i32(i32fld(ctx->opcode)); \ >> gen_helper_##name(cpu_env, rt, ra, rb, i32); \ >> if (unlikely(Rc(ctx->opcode) != 0)) { \ >> - gen_set_cr6_from_fpscr(ctx); \ >> + gen_set_cr1_from_fpscr(ctx); \ >> } \ >> tcg_temp_free_ptr(rt); \ >> tcg_temp_free_ptr(rb); \ >> @@ -8310,7 +8310,7 @@ static void gen_##name(DisasContext *ctx) \ >> rb = gen_fprp_ptr(rB(ctx->opcode)); \ >> gen_helper_##name(cpu_env, rt, rb); \ >> if (unlikely(Rc(ctx->opcode) != 0)) { \ >> - gen_set_cr6_from_fpscr(ctx); \ >> + gen_set_cr1_from_fpscr(ctx); \ >> } \ >> tcg_temp_free_ptr(rt); \ >> tcg_temp_free_ptr(rb); \ >> @@ -8331,7 +8331,7 @@ static void gen_##name(DisasContext *ctx) \ >> i32 = tcg_const_i32(i32fld(ctx->opcode)); \ >> gen_helper_##name(cpu_env, rt, rs, i32); \ >> if (unlikely(Rc(ctx->opcode) != 0)) { \ >> - gen_set_cr6_from_fpscr(ctx); \ >> + gen_set_cr1_from_fpscr(ctx); \ >> } \ >> tcg_temp_free_ptr(rt); \ >> tcg_temp_free_ptr(rs); \ >> > > Reviewed-by: Tom Musta > Tested-by: Tom Musta Thanks, applied to ppc-next. Alex