From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755236AbaIHXiF (ORCPT ); Mon, 8 Sep 2014 19:38:05 -0400 Received: from g4t3425.houston.hp.com ([15.201.208.53]:46342 "EHLO g4t3425.houston.hp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753308AbaIHXiD (ORCPT ); Mon, 8 Sep 2014 19:38:03 -0400 Message-ID: <540E3D60.2020906@hp.com> Date: Mon, 08 Sep 2014 19:36:00 -0400 From: Waiman Long User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.12) Gecko/20130109 Thunderbird/10.0.12 MIME-Version: 1.0 To: Pranith Kumar CC: LKML Subject: Re: Question reg. asm/qrwlock.h References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/05/2014 07:45 PM, Pranith Kumar wrote: > Hi Waiman, > > I see that in arch/x86/include/asm/qrwlock.h, there is this snippet within > > #ifndef CONFIG_X86_PPRO_FENCE > #define queue_write_unlock queue_write_unlock > static inline void queue_write_unlock(struct qrwlock *lock) > { > barrier(); > ACCESS_ONCE(*(u8 *)&lock->cnts) = 0; > } > #endif > > > I've been trying to understand why this special case is necessary for > PPRO. Could you please explain? > > Thanks! This is related to the memory ordering of the x86 architecture. Modern x86 processor has pretty strong memory ordering semantics where only stores can be reordered after load. So a barrier() call is a good enough memory barrier except for some older x86 processors (Pentium Pro) that should have CONFIG_X86_PPRO_FENCE set. In that case, atomic instruction like cmpxchg() will be needed to ensure proper memory ordering. -Longman