From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?windows-1252?Q?Michel_D=E4nzer?= Subject: Re: [PATCH] drm/radeon: Add RADEON_GEM_CPU_ACCESS BO creation flag Date: Tue, 09 Sep 2014 10:15:52 +0900 Message-ID: <540E54C8.8030500@daenzer.net> References: <1409208961-7322-1-git-send-email-michel@daenzer.net> <53FEEEF4.7030401@vodafone.de> <53FFDB6B.5050105@daenzer.net> <540E4E28.50701@daenzer.net> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <540E4E28.50701@daenzer.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: mesa-dev-bounces@lists.freedesktop.org Sender: "mesa-dev" To: Alex Deucher Cc: "mesa-dev@lists.freedesktop.org" , Maling list - DRI developers List-Id: dri-devel@lists.freedesktop.org On 09.09.2014 09:47, Michel D=E4nzer wrote: > On 09.09.2014 02:36, Alex Deucher wrote: >> >> Updated version with comments integrated. > = > [...] > = >> @@ -314,10 +314,12 @@ int radeon_bo_pin_restricted(struct radeon_bo = >> *bo, u32 domain, u64 max_offset, >> unsigned lpfn =3D 0; >> >> /* force to pin into visible video ram */ >> - if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) >> - lpfn =3D bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; >> - else >> + if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) { >> + if (!(bo->flags & RADEON_GEM_NO_CPU_ACCESS)) >> + lpfn =3D bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; >> + } else { >> lpfn =3D bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */ >> + } > = > The else block can be removed as well, but that can be done in another = > patch. Actually, I just noticed a problem, the following if statement: > if (max_offset) > lpfn =3D min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT)); This will ignore max_offset if lpfn is 0. So either go with v1 of this hunk, or rebase on top of the patch below. From: =3D?UTF-8?q?Michel=3D20D=3DC3=3DA4nzer?=3D Date: Tue, 9 Sep 2014 10:09:23 +0900 Subject: [PATCH] drm/radeon: Clean up assignment of TTM placement lpfn memb= er for pinning MIME-Version: 1.0 Content-Type: text/plain; charset=3DUTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michel D=E4nzer --- drivers/gpu/drm/radeon/radeon_object.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeo= n/radeon_object.c index 908ea541..8ec8150 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -307,18 +307,14 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u3= 2 domain, u64 max_offset, } radeon_ttm_placement_from_domain(bo, domain); for (i =3D 0; i < bo->placement.num_placement; i++) { - unsigned lpfn =3D 0; - /* force to pin into visible video ram */ if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) - lpfn =3D bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; + bo->placements[i].lpfn =3D + min(bo->rdev->mc.visible_vram_size, max_offset) + >> PAGE_SHIFT; else - lpfn =3D bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */ - - if (max_offset) - lpfn =3D min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT)); + bo->placements[i].lpfn =3D max_offset >> PAGE_SHIFT; = - bo->placements[i].lpfn =3D lpfn; bo->placements[i].flags |=3D TTM_PL_FLAG_NO_EVICT; } = -- = 2.1.0 -- = Earthling Michel D=E4nzer | http://www.amd.com Libre software enthusiast | Mesa and X developer