From: Alexander Graf <agraf@suse.de>
To: Pierre Mallard <mallard.pierre@gmail.com>,
qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: agraf@suze.de, tommusta@gmail.com
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 0/2] Enabling floating point instruction to 440x5 CPUs
Date: Fri, 12 Sep 2014 21:46:40 +0200 [thread overview]
Message-ID: <54134DA0.5080700@suse.de> (raw)
In-Reply-To: <1410550293-3814-1-git-send-email-mallard.pierre@gmail.com>
On 12.09.14 21:31, Pierre Mallard wrote:
> This patch series enable floating point instruction in 440x5 CPUs
> which have the capabilities to have optional APU FPU in double precision mode.
>
> 1) Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 with a new insn2 flag
> 2) Create a new 440x5 implementing floating point instructions
Thanks, applied to ppc-next.
Alex
prev parent reply other threads:[~2014-09-12 19:46 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1410325413>
2014-09-11 19:17 ` [Qemu-devel] [PATCH 0/2] Enabling floating point instruction to 440x5 CPUs Pierre Mallard
2014-09-11 19:17 ` [Qemu-devel] [PATCH 1/2] target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 Pierre Mallard
2014-09-12 14:28 ` Tom Musta
2014-09-12 14:40 ` Tom Musta
2014-09-12 14:56 ` Alexander Graf
2014-09-11 19:17 ` [Qemu-devel] [PATCH 2/2] target-ppc : Add new processor type 440x5wDFPU Pierre Mallard
2014-09-12 14:41 ` Tom Musta
2014-09-12 14:29 ` [Qemu-devel] [PATCH 0/2] Enabling floating point instruction to 440x5 CPUs Tom Musta
2014-09-12 19:27 ` Pierre Mallard
2014-09-12 19:31 ` [Qemu-devel] [PATCH v2 " Pierre Mallard
2014-09-12 19:31 ` [Qemu-devel] [PATCH v2 1/2] target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 Pierre Mallard
2014-09-12 19:31 ` [Qemu-devel] [PATCH v2 2/2] target-ppc : Add new processor type 440x5wDFPU Pierre Mallard
2014-09-12 19:46 ` Alexander Graf [this message]
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