From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33206) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XU1AN-0001zb-QS for qemu-devel@nongnu.org; Tue, 16 Sep 2014 18:24:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XU1AE-0006jg-Nt for qemu-devel@nongnu.org; Tue, 16 Sep 2014 18:24:07 -0400 Received: from mail-qa0-x235.google.com ([2607:f8b0:400d:c00::235]:52194) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XU1AE-0006ia-J9 for qemu-devel@nongnu.org; Tue, 16 Sep 2014 18:23:58 -0400 Received: by mail-qa0-f53.google.com with SMTP id n8so745836qaq.12 for ; Tue, 16 Sep 2014 15:23:55 -0700 (PDT) Sender: Richard Henderson Message-ID: <5418B877.8080308@twiddle.net> Date: Tue, 16 Sep 2014 15:23:51 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1410793421-6453-1-git-send-email-pbonzini@redhat.com> <1410793421-6453-4-git-send-email-pbonzini@redhat.com> <5418716A.9080508@gmail.com> <54187B3D.8000909@twiddle.net> <5418810E.3080100@redhat.com> <5418846E.8070608@twiddle.net> In-Reply-To: <5418846E.8070608@twiddle.net> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for various translation modes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Tom Musta , Peter Maydell On 09/16/2014 11:41 AM, Richard Henderson wrote: >> In practice, only 3 to 7 are---hence my original attempt at using some >> kind of FIFO caching: >> >> user mode, translation enabled >> kernel mode, paging disabled >> kernel mode, paging enabled >> supervisor mode, paging disabled >> supervisor mode, paging enabled >> >> Plus perhaps kernel and supervisor mode with only data paging enabled. >> >> You could lump together the IR!=0, DR!=0 cases, and flush that one TLB >> index if the IR/DR pair changes with respect to the last time. This >> would use 6 indices. > > I think I would prefer a solution that uses 6 indicies, as will not cause env > to overflow 64k, and not require that any tcg backends be updated. ... alternately ... What if instead of having a "mmu_index" for the mmu arrays, we have a pointer to the "mmu context". This does imply an extra memory load on the fast path, but probably not an extra instruction. With this, we can suddenly afford to have a relatively large number of mmu contexts, with which we could implement address space numbers for relevant targets. It is, of course, a much larger change, but perhaps it's of larger benefit. r~