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Subject: Re: [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for
 various translation modes
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To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>, Tom Musta <tommusta@gmail.com>, qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>, qemu-devel@nongnu.org

On 09/17/2014 01:53 AM, Paolo Bonzini wrote:
> +/* All the TLBs together must be smaller than 64k on RISC machines  */
> +#if !defined(__i386__) && !defined(__x86_64__) && !defined(__aarch64__) \
> +    && !defined(__sparc__) && !defined(CONFIG_TCG_INTERPRETER)
> +#define CPU_TLB_BITS (NB_MMU_MODES < 8 ? 8 : 12 - CPU_TLB_ENTRY_BITS)
> +#else
> +#define CPU_TLB_BITS 8
> +#endif

Hum.  Well, it's not that all the tlbs together that must be less than 64k,
it's the addend of the first entry of the last tlb that must be within 64k of
the start of env.  Nit picking, but perhaps we can word the comment better.

And if we choose to do something like this, this is where I'd prefer a define
in the relevant tcg-target.h.  Because you've missed ia64 and s390 that have
positive offsets larger than 64k (21 and 19 bits, respectively).

But otherwise I'm ok with this as a solution.


r~