From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36317) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XUHZ6-0007AY-7b for qemu-devel@nongnu.org; Wed, 17 Sep 2014 11:54:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XUHYy-0006mq-A6 for qemu-devel@nongnu.org; Wed, 17 Sep 2014 11:54:44 -0400 Received: from thoth.sbs.de ([192.35.17.2]:52646) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XUHYx-0006mJ-W9 for qemu-devel@nongnu.org; Wed, 17 Sep 2014 11:54:36 -0400 Message-ID: <5419AEB4.3020608@siemens.com> Date: Wed, 17 Sep 2014 17:54:28 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <1408643079-30675-1-git-send-email-jsnow@redhat.com> <1408643079-30675-3-git-send-email-jsnow@redhat.com> In-Reply-To: <1408643079-30675-3-git-send-email-jsnow@redhat.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 2/8] ahci: MSI capability should be at 0x80, not 0x50. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: John Snow , qemu-devel@nongnu.org Cc: armbru@redhat.com, stefanha@redhat.com, mst@redhat.com On 2014-08-21 19:44, John Snow wrote: > In the Intel ICH9 data sheet, the MSI capability offset > in the PCI configuration space for ICH9 AHCI devices is > specified to be 0x80. > > Further, the PCI capability pointer should always point > to 0x80 in ICH9 devices, despite the fact that AHCI 1.3 > specifies that it should be pointing to PMCAP (Which in > this instance would be 0x70) to maintain adherence to > the Intel data sheet specifications and real observed behavior. > > Signed-off-by: John Snow > --- > hw/ide/ich.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/hw/ide/ich.c b/hw/ide/ich.c > index a2f1639..8eb77a1 100644 > --- a/hw/ide/ich.c > +++ b/hw/ide/ich.c > @@ -71,6 +71,7 @@ > #include > #include > > +#define ICH9_MSI_CAP_OFFSET 0x80 > #define ICH9_SATA_CAP_OFFSET 0xA8 > > #define ICH9_IDP_BAR 4 > @@ -115,7 +116,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev) > /* XXX Software should program this register */ > dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ > > - msi_init(dev, 0x50, 1, true, false); > d->ahci.irq = pci_allocate_irq(dev); > > pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO, > @@ -135,6 +135,11 @@ static int pci_ich9_ahci_init(PCIDevice *dev) > (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4)); > d->ahci.idp_offset = ICH9_IDP_INDEX; > > + /* Although the AHCI 1.3 specification states that the first capability > + * should be PMCAP, the Intel ICH9 data sheet specifies that the ICH9 > + * AHCI device puts the MSI capability first, pointing to 0x80. */ > + msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false); > + > return 0; > } > > I did this for HDA recently, and it became clear that this requires a compat switch to expose the old, broken layout to older guests. Otherwise you can't migrate from them. Jan -- Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux