From: Tomasz Figa <tomasz.figa@gmail.com>
To: Marek Szyprowski <m.szyprowski@samsung.com>,
linux-samsung-soc@vger.kernel.org
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Subject: Re: [PATCH] clk: exynos4: fix g3d clocks
Date: Mon, 22 Sep 2014 14:32:57 +0200 [thread overview]
Message-ID: <542016F9.9090306@gmail.com> (raw)
In-Reply-To: <1411388232-6271-1-git-send-email-m.szyprowski@samsung.com>
On 22.09.2014 14:17, Marek Szyprowski wrote:
> sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked
> g3d gate clock bits for this purpose and didn't provide real g3d clock
> at all. This patch fixes this issue by adding proper definition for g3d
> clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos4.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
Applied for next with a minor adjustment of patch description.
Best regards,
Tomasz
prev parent reply other threads:[~2014-09-22 12:33 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-22 12:17 [PATCH] clk: exynos4: fix g3d clocks Marek Szyprowski
2014-09-22 12:32 ` Tomasz Figa [this message]
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