Re: [PATCH v4] can: flexcan: Re-write receive path to use MB queue instead of FIFO

[Marc Kleine-Budde <mkl@pengutronix.de>]

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On 09/23/2014 02:58 PM, Marc Kleine-Budde wrote:
> On 09/18/2014 03:48 PM, David Jander wrote:
>> > The FlexCAN controller has a RX FIFO that is only 6 messages deep, and a
>> > mailbox space capable of holding up to 63 messages.
>> > This space was largely unused, limiting the permissible latency from
>> > interrupt to NAPI to only 6 messages. This patch uses all available MBs
>> > for message reception and frees the MBs in the IRQ handler to greatly
>> > decrease the likelihood of receive overruns.
>> > 
>> > Signed-off-by: David Jander <david@protonic.nl>
> I think we can improve the algorithm a bit.
> 
> I see a problem when you receive 4 CAN frames:
> 
> 0-1-2-3
> 
> then the irq handler starts, 0 gets processed and is empty (E)
> 
> E-1-2-3
> 
> while in the interrupt handler another two frames come in:
> 
> 4-1-2-3-5
> 
> I suggest add a variable to the priv which indicates the next MB to read
> from. Further, don't clear the mailbox direclty after it's been read,
> wait until a certain amount of read mailboxes accumulate, .e.g. when the
> rx_next point to 32. I have a work-in-progress code which to abstract
> this algorithm, but it limited to 32 mailboxes. It should work on the
> at91 but I don't know if it's flexible enought yet to work on the
> flexcan, too.

For the algorithm see the rx-fifo branch on linux-can-next. Feel free to
comment.

Marc

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