From: Jacek Danecki <jacek.danecki@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATH] Correct GPU timestamp read
Date: Tue, 23 Sep 2014 19:12:31 +0200 [thread overview]
Message-ID: <5421A9FF.3000909@intel.com> (raw)
In-Reply-To: <20140923083726.GY15734@phenom.ffwll.local>
On 09/23/14 10:37, Daniel Vetter wrote:
> On Mon, Sep 22, 2014 at 06:22:53PM +0200, Jacek Danecki wrote:
>> Current implementation of reading GPU timestamp is broken.
>> It returns lower 32 bits shifted by 32 bits (XXXXXXXX00000000 instead of YYYYYYYYXXXXXXXX).
>> Below change is adding possibility to read hi part of that register separately.
>>
>> Signed-off-by: Jacek Danecki jacek.danecki@intel.com
>
> Needs to come with corresponding userspace using this.
Beignet can use this in below function. They are using only 32 bits from timestamp register, because of kernel bug.
* IVB and HSW's result MUST shift in x86_64 system */
static uint64_t
intel_gpgpu_read_ts_reg_gen7(drm_intel_bufmgr *bufmgr)
{
uint64_t result = 0;
drm_intel_reg_read(bufmgr, TIMESTAMP_ADDR, &result);
/* In x86_64 system, the low 32bits of timestamp count are stored in the high 32 bits of
result which got from drm_intel_reg_read, and 32-35 bits are lost; but match bspec in
i386 system. It seems the kernel readq bug. So shift 32 bit in x86_64, and only remain
32 bits data in i386.
*/
#ifdef __i386__
return result & 0x0ffffffff;
#else
return result >> 32;
#endif /* __i386__ */
}
--
jacek
next prev parent reply other threads:[~2014-09-23 17:12 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-22 16:22 [PATH] Correct GPU timestamp read Jacek Danecki
2014-09-23 8:37 ` Daniel Vetter
2014-09-23 17:12 ` Jacek Danecki [this message]
2014-09-25 12:26 ` Chris Wilson
2014-09-25 13:00 ` Jacek Danecki
2014-09-25 13:09 ` Chris Wilson
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