From mboxrd@z Thu Jan 1 00:00:00 1970 From: cov@codeaurora.org (Christopher Covington) Date: Mon, 29 Sep 2014 09:12:26 -0400 Subject: [PATCH v3] clocksource: arch_timer: Allow the device tree to specify the physical timer In-Reply-To: <1410454801-14231-1-git-send-email-dianders@chromium.org> References: <1410454801-14231-1-git-send-email-dianders@chromium.org> Message-ID: <54295ABA.1010806@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Doug, On 09/11/2014 01:00 PM, Doug Anderson wrote: > Some 32-bit (ARMv7) systems are architected like this: > > * The firmware doesn't know and doesn't care about hypervisor mode and > we don't want to add the complexity of hypervisor there. > > * The firmware isn't involved in SMP bringup or resume. > > * The ARCH timer come up with an uninitialized offset between the > virtual and physical counters. Each core gets a different random > offset. > > * The device boots in "Secure SVC" mode. I believe this can safely be detected by whether a write to CNTFRQ succeeds (handling the UNDEF on failure). I've tested this approach in what I've determined to be the 19 valid combinations of the following options. * AArch64 EL3, AArch32 EL3, no EL3 * AArch64 EL2, AArch32 EL2, no EL2 * Start in SVC_N, SVC_S, HYP_N, MON_S Christopher -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by the Linux Foundation. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christopher Covington Subject: Re: [PATCH v3] clocksource: arch_timer: Allow the device tree to specify the physical timer Date: Mon, 29 Sep 2014 09:12:26 -0400 Message-ID: <54295ABA.1010806@codeaurora.org> References: <1410454801-14231-1-git-send-email-dianders@chromium.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1410454801-14231-1-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Doug Anderson Cc: olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Lorenzo Pieralisi , Daniel Lezcano , pawel.moll-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, Marc Zyngier , Stephen Boyd , Sudeep Holla , Will Deacon , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Catalin Marinas , Nathan Lynch , Thomas Gleixner , Sonny Rao , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org Hi Doug, On 09/11/2014 01:00 PM, Doug Anderson wrote: > Some 32-bit (ARMv7) systems are architected like this: > > * The firmware doesn't know and doesn't care about hypervisor mode and > we don't want to add the complexity of hypervisor there. > > * The firmware isn't involved in SMP bringup or resume. > > * The ARCH timer come up with an uninitialized offset between the > virtual and physical counters. Each core gets a different random > offset. > > * The device boots in "Secure SVC" mode. I believe this can safely be detected by whether a write to CNTFRQ succeeds (handling the UNDEF on failure). I've tested this approach in what I've determined to be the 19 valid combinations of the following options. * AArch64 EL3, AArch32 EL3, no EL3 * AArch64 EL2, AArch32 EL2, no EL2 * Start in SVC_N, SVC_S, HYP_N, MON_S Christopher -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by the Linux Foundation. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754037AbaI2NMc (ORCPT ); Mon, 29 Sep 2014 09:12:32 -0400 Received: from smtp.codeaurora.org ([198.145.11.231]:35036 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752177AbaI2NMa (ORCPT ); Mon, 29 Sep 2014 09:12:30 -0400 Message-ID: <54295ABA.1010806@codeaurora.org> Date: Mon, 29 Sep 2014 09:12:26 -0400 From: Christopher Covington User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-Version: 1.0 To: Doug Anderson CC: olof@lixom.net, mark.rutland@arm.com, devicetree@vger.kernel.org, Lorenzo Pieralisi , Daniel Lezcano , pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, Marc Zyngier , Stephen Boyd , Sudeep Holla , Will Deacon , linux-kernel@vger.kernel.org, galak@codeaurora.org, robh+dt@kernel.org, Catalin Marinas , Nathan Lynch , Thomas Gleixner , Sonny Rao , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3] clocksource: arch_timer: Allow the device tree to specify the physical timer References: <1410454801-14231-1-git-send-email-dianders@chromium.org> In-Reply-To: <1410454801-14231-1-git-send-email-dianders@chromium.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Doug, On 09/11/2014 01:00 PM, Doug Anderson wrote: > Some 32-bit (ARMv7) systems are architected like this: > > * The firmware doesn't know and doesn't care about hypervisor mode and > we don't want to add the complexity of hypervisor there. > > * The firmware isn't involved in SMP bringup or resume. > > * The ARCH timer come up with an uninitialized offset between the > virtual and physical counters. Each core gets a different random > offset. > > * The device boots in "Secure SVC" mode. I believe this can safely be detected by whether a write to CNTFRQ succeeds (handling the UNDEF on failure). I've tested this approach in what I've determined to be the 19 valid combinations of the following options. * AArch64 EL3, AArch32 EL3, no EL3 * AArch64 EL2, AArch32 EL2, no EL2 * Start in SVC_N, SVC_S, HYP_N, MON_S Christopher -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by the Linux Foundation.