From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZdVw-0000zG-JK for qemu-devel@nongnu.org; Thu, 02 Oct 2014 06:21:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZdVs-0004QY-0Z for qemu-devel@nongnu.org; Thu, 02 Oct 2014 06:21:36 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:1407) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZdVr-0004Pj-Qj for qemu-devel@nongnu.org; Thu, 02 Oct 2014 06:21:31 -0400 Message-ID: <542D2727.6010902@imgtec.com> Date: Thu, 2 Oct 2014 11:21:27 +0100 From: Yongbok Kim MIME-Version: 1.0 References: <1403882530-47821-1-git-send-email-leon.alrae@imgtec.com> <1403882530-47821-19-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1403882530-47821-19-git-send-email-leon.alrae@imgtec.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 18/21] target-mips: do not allow Status.FR=0 mode in 64-bit FPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae Cc: cristian.cuna@imgtec.com, qemu-devel@nongnu.org, aurelien@aurel32.net, rth@twiddle.net There is a block of code that modifies CP0_Status_rw_bitmask.CP0St_FR bit to read-writable in the same function. So effectively in case of MIPS64 R6 the bit is now R/W which shouldn't be. You need to modify or merge the code. # if defined(TARGET_MIPS64) /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ if ((env->CP0_Config1 & (1 << CP0C1_FP)) && (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { env->CP0_Status |= (1 << CP0St_FR); } # endif Regards, Yongbok On 27/06/14 16:22, Leon Alrae wrote: > Status.FR bit must be ignored on write and read as 1 when an implementation of > Release 6 of the Architecture in which a 64-bit floating point unit is > implemented. > > Signed-off-by: Leon Alrae > --- > v3: > * remove line modifying CP0_Status_rw_bitmask as this is done while defining > CPU > --- > target-mips/translate.c | 6 ++++++ > 1 files changed, 6 insertions(+), 0 deletions(-) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index a804322..7cfda3d 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -17942,6 +17942,12 @@ void cpu_state_reset(CPUMIPSState *env) > } > } > #endif > + if ((env->insn_flags & ISA_MIPS32R6) && > + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { > + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ > + env->CP0_Status |= (1 << CP0St_FR); > + } > + > compute_hflags(env); > cs->exception_index = EXCP_NONE; > }