From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH] AMD/guest_iommu: Disable guest iommu support
Date: Thu, 2 Oct 2014 15:08:10 +0100
Message-ID: <542D5C4A.3050609@citrix.com>
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Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>, Roberto Luongo <rluongo@ready.it>, Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>, Jan Beulich <JBeulich@suse.com>
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On 02/10/14 15:02, Andrew Cooper wrote:
> AMD Guest IOMMU support was added to allow correct use of PASID and PRI
> hardware support with an ATS-aware guest driver.
>
> However, support cannot possibly function as guest_iommu_set_base() has no
> callers.  This means that its MMIO region's P2M pages are not set to
> p2m_mmio_dm, preventing any invocation of the MMIO read/write handlers.
>
> c/s fd186384 "x86/HVM: extend LAPIC shortcuts around P2M lookups" introduces a
> path (via hvm_mmio_internal()) where iommu_mmio_handler claims its MMIO range,
> and causes __hvm_copy() to fail with HVMCOPY_bad_gfn_to_mfn.
>
> iommu->mmio_base defaults to 0, with a range of 8 pages, and is unilaterally
> enabled in any HVM guests when the host IOMMU(s) supports any extended
> features.
>
> Unfortunately, HVMLoader's AP boot trampoline executes an `lmsw` instruction
> at linear address 0x100c which unconditionally requires emulation.  The
> instruction fetch in turn fails as __hvm_copy() fails with
> HVMCOPY_bad_gfn_to_mfn.
>
> The result is that multi-vcpu HVM guests do not work on newer AMD hardware, if
> IOMMU support is enabled in the BIOS.
>
> Change the default mmio_base address to ~0ULL.  This prevents
> guest_iommu_mmio_range() from actually claiming any physical range
> whatsoever, which allows the emulation of `lmsw` to succeed.
>
> Reported-by: Roberto Luongo <rluongo@ready.it>
> Suggested-by: Jan Beulich <JBeulich@suse.com>
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
> Tested-by: Roberto Luongo <rluongo@ready.it>
> CC: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> CC: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
> ---

I forgot to explicitly indicate, but this is a bugfix and is therefore
intended for inclusion in 4.5

~Andrew