From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Greg Bellows <greg.bellows@linaro.org>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Sergey Fedorov <s.fedorov@samsung.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Fabian Aggeler <aggelerf@ethz.ch>
Subject: Re: [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function
Date: Mon, 06 Oct 2014 10:57:46 -0700 [thread overview]
Message-ID: <5432D81A.2080200@gmail.com> (raw)
In-Reply-To: <CAFEAcA8zhd_V902y066KszE_qZXzC4azegXDFmHuPbqOVg-pYg@mail.gmail.com>
On 06.10.2014 07:56, Peter Maydell wrote:
> On 30 September 2014 22:49, Greg Bellows <greg.bellows@linaro.org> wrote:
>> From: Fabian Aggeler <aggelerf@ethz.ch>
>>
>> arm_is_secure() function allows to determine CPU security state
>> if the CPU implements Security Extensions/EL3.
>> arm_is_secure_below_el3() returns true if CPU is in secure state
>> below EL3.
>>
>> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
>> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
>> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
>> ---
>> target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 38 insertions(+)
>>
>> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
>> index 81fffd2..10afef0 100644
>> --- a/target-arm/cpu.h
>> +++ b/target-arm/cpu.h
>> @@ -753,6 +753,44 @@ static inline int arm_feature(CPUARMState *env, int feature)
>> return (env->features & (1ULL << feature)) != 0;
>> }
>>
>> +
>> +/* Return true if exception level below EL3 is in secure state */
>> +static inline bool arm_is_secure_below_el3(CPUARMState *env)
>> +{
>> +#if !defined(CONFIG_USER_ONLY)
>> + if (arm_feature(env, ARM_FEATURE_EL3)) {
>> + return !(env->cp15.scr_el3 & SCR_NS);
>> + } else if (arm_feature(env, ARM_FEATURE_EL2)) {
>> + return false;
>> + } else {
>> + /* IMPDEF: QEMU defaults to non-secure */
>> + return false;
> I would be happy to fold both these identical 'return false'
> cases together and have a comment that it's only IMPDEF
> if EL2 isn't implemented.
>
>> + }
>> +#else
>> + return false;
>> +#endif
>> +}
>> +
>> +/* Return true if the processor is in secure state */
>> +static inline bool arm_is_secure(CPUARMState *env)
>> +{
>> +#if !defined(CONFIG_USER_ONLY)
>> + if (arm_feature(env, ARM_FEATURE_EL3)) {
>> + if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) {
>> + /* CPU currently in Aarch64 state and EL3 */
> Nit: "AArch64" with two capital 'A's (here and elsewhere).
>
>> + return true;
>> + } else if (!env->aarch64 &&
>> + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
>> + /* CPU currently in Aarch32 state and monitor mode */
>> + return true;
>> + }
>> + }
>> + return arm_is_secure_below_el3(env);
>> +#else
>> + return false;
>> +#endif
>> +}
> I checked your git tree and we don't actually use
> arm_is_secure_below_el3() anywhere except in
> arm_is_secure(), do we? That suggests to me we should
> just fold the two functions together.
>
> Can these functions live in internals.h rather than cpu.h?
> (The difference is that internals.h is restricted to only
> target-arm/ code whereas cpu.h is auto-included for a much
> wider set of files.)
Probably arm_is_secure() would be used by ARM GIC emulation until there
is no better way to determine memory transaction NS tag.
>
> thanks
> -- PMM
next prev parent reply other threads:[~2014-10-06 17:58 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-30 21:49 [Qemu-devel] [PATCH v5 00/33] target-arm: add Security Extensions for CPUs Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 01/33] target-arm: increase arrays of registers R13 & R14 Greg Bellows
2014-10-06 14:48 ` Peter Maydell
2014-10-06 19:21 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function Greg Bellows
2014-09-30 22:50 ` Edgar E. Iglesias
2014-10-01 12:53 ` Greg Bellows
2014-10-06 14:56 ` Peter Maydell
2014-10-06 17:57 ` Sergey Fedorov [this message]
2014-10-06 18:01 ` Peter Maydell
2014-10-06 19:45 ` Greg Bellows
2014-10-06 20:07 ` Peter Maydell
2014-10-06 20:47 ` Greg Bellows
2014-10-06 21:07 ` Peter Maydell
2014-10-08 19:33 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 03/33] target-arm: reject switching to monitor mode Greg Bellows
2014-10-06 15:02 ` Peter Maydell
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 04/33] target-arm: rename arm_current_pl to arm_current_el Greg Bellows
2014-09-30 22:56 ` Edgar E. Iglesias
2014-10-01 12:54 ` Greg Bellows
2014-10-06 15:10 ` Peter Maydell
2014-10-06 19:55 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 05/33] target-arm: make arm_current_pl() return PL3 Greg Bellows
2014-10-01 1:23 ` Sergey Fedorov
2014-10-01 14:31 ` Greg Bellows
2014-10-06 15:34 ` Peter Maydell
2014-10-06 20:53 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 06/33] target-arm: A32: Emulate the SMC instruction Greg Bellows
2014-10-06 15:46 ` Peter Maydell
2014-10-07 1:56 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 07/33] target-arm: extend async excp masking Greg Bellows
2014-10-06 15:53 ` Peter Maydell
2014-10-07 3:16 ` Greg Bellows
2014-10-07 7:03 ` Peter Maydell
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 08/33] target-arm: add async excp target_el function Greg Bellows
2014-10-06 16:02 ` Peter Maydell
2014-10-07 3:52 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 09/33] target-arm: add macros to access banked registers Greg Bellows
2014-10-06 16:09 ` Peter Maydell
2014-10-07 4:02 ` Greg Bellows
2014-10-07 6:54 ` Peter Maydell
2014-10-07 17:49 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 10/33] target-arm: add non-secure Translation Block flag Greg Bellows
2014-10-06 16:13 ` Peter Maydell
2014-10-06 18:10 ` Sergey Fedorov
2014-10-07 4:21 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 11/33] target-arm: arrayfying fieldoffset for banking Greg Bellows
2014-10-06 16:19 ` Peter Maydell
2014-10-07 5:06 ` Greg Bellows
2014-10-07 7:12 ` Peter Maydell
2014-10-07 21:50 ` Greg Bellows
2014-10-07 22:38 ` Peter Maydell
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 12/33] target-arm: insert Aarch32 cpregs twice into hashtable Greg Bellows
2014-10-06 16:25 ` Peter Maydell
2014-10-07 5:31 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 13/33] target-arm: move Aarch32 SCR into security reglist Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 14/33] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 15/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 16/33] target-arm: add NSACR register Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 17/33] target-arm: add SDER definition Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 18/33] target-arm: add MVBAR support Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 19/33] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 20/33] target-arm: make CSSELR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 21/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 22/33] target-arm: add TCR_EL3 and make TTBCR banked Greg Bellows
2014-09-30 23:18 ` Edgar E. Iglesias
2014-10-01 13:05 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 24/33] target-arm: make DACR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 25/33] target-arm: make IFSR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 26/33] target-arm: make DFSR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 27/33] target-arm: make IFAR/DFAR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 28/33] target-arm: make PAR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 29/33] target-arm: make VBAR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 30/33] target-arm: make MAIR0/1 banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 31/33] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-10-01 14:30 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 32/33] target-arm: add GDB scr register Greg Bellows
2014-10-06 16:27 ` Peter Maydell
2014-10-07 5:09 ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 33/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows
2014-10-06 16:28 ` Peter Maydell
2014-10-06 16:32 ` [Qemu-devel] [PATCH v5 00/33] target-arm: add Security Extensions for CPUs Peter Maydell
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