From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Ostrovsky Subject: Re: [PATCH v13 for-xen-4.5 07/21] x86/VPMU: Handle APIC_LVTPC accesses Date: Mon, 13 Oct 2014 14:05:26 -0400 Message-ID: <543C1466.6050309@oracle.com> References: <1412372423-1182-1-git-send-email-boris.ostrovsky@oracle.com> <1412372423-1182-8-git-send-email-boris.ostrovsky@oracle.com> <543BE970020000780003E4BD@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <543BE970020000780003E4BD@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: kevin.tian@intel.com, keir@xen.org, suravee.suthikulpanit@amd.com, andrew.cooper3@citrix.com, tim@xen.org, dietmar.hahn@ts.fujitsu.com, xen-devel@lists.xen.org, Aravind.Gopalakrishnan@amd.com, jun.nakajima@intel.com, dgdegra@tycho.nsa.gov List-Id: xen-devel@lists.xenproject.org On 10/13/2014 09:02 AM, Jan Beulich wrote: >>>> On 03.10.14 at 23:40, wrote: >> @@ -706,10 +693,6 @@ static int core2_vpmu_do_interrupt(struct cpu_user_regs *regs) >> return 0; >> } >> >> - /* HW sets the MASK bit when performance counter interrupt occurs*/ >> - vpmu->hw_lapic_lvtpc = apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED; >> - apic_write_around(APIC_LVTPC, vpmu->hw_lapic_lvtpc); > So why is simply deleting this correct? The comment makes pretty > clear why it was being done here. All I could see being valid without > further explanation is the removal of the middle of the three lines. It is expected that PMU interrupt will set the mask bit so whoever is using PMU hardware (bare-metal or virtualized) is expected to clear it. Therefore there is no reason for the hypervisor to do this. I can add a note about it in the commit message. -boris