From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41425) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xe4RZ-0006ZE-CP for qemu-devel@nongnu.org; Tue, 14 Oct 2014 11:55:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xe4RU-0008FK-3t for qemu-devel@nongnu.org; Tue, 14 Oct 2014 11:55:25 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:4256) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xe4RT-0008F9-Tq for qemu-devel@nongnu.org; Tue, 14 Oct 2014 11:55:20 -0400 Message-ID: <543D4763.9050401@imgtec.com> Date: Tue, 14 Oct 2014 16:55:15 +0100 From: Yongbok Kim MIME-Version: 1.0 References: <1404806257-28048-1-git-send-email-leon.alrae@imgtec.com> <1404806257-28048-4-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1404806257-28048-4-git-send-email-leon.alrae@imgtec.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 3/9] target-mips: distinguish between data load and instruction fetch List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae , qemu-devel@nongnu.org Cc: aurelien@aurel32.net Reviewed-by: Yongbok Kim On 08/07/2014 08:57, Leon Alrae wrote: > Signed-off-by: Leon Alrae > --- > target-mips/helper.c | 21 ++++++++++----------- > 1 files changed, 10 insertions(+), 11 deletions(-) > > diff --git a/target-mips/helper.c b/target-mips/helper.c > index 8a997e4..9871273 100644 > --- a/target-mips/helper.c > +++ b/target-mips/helper.c > @@ -87,7 +87,7 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, > /* Check access rights */ > if (!(n ? tlb->V1 : tlb->V0)) > return TLBRET_INVALID; > - if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { > + if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { > *physical = tlb->PFN[n] | (address & (mask >> 1)); > *prot = PAGE_READ; > if (n ? tlb->D1 : tlb->D0) > @@ -237,25 +237,28 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, > case TLBRET_BADADDR: > /* Reference to kernel address from user mode or supervisor mode */ > /* Reference to supervisor address from user mode */ > - if (rw) > + if (rw == MMU_DATA_STORE) { > exception = EXCP_AdES; > - else > + } else { > exception = EXCP_AdEL; > + } > break; > case TLBRET_NOMATCH: > /* No TLB match for a mapped address */ > - if (rw) > + if (rw == MMU_DATA_STORE) { > exception = EXCP_TLBS; > - else > + } else { > exception = EXCP_TLBL; > + } > error_code = 1; > break; > case TLBRET_INVALID: > /* TLB match with no valid bit */ > - if (rw) > + if (rw == MMU_DATA_STORE) { > exception = EXCP_TLBS; > - else > + } else { > exception = EXCP_TLBL; > + } > break; > case TLBRET_DIRTY: > /* TLB match but 'D' bit is cleared */ > @@ -312,8 +315,6 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, > qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", > __func__, env->active_tc.PC, address, rw, mmu_idx); > > - rw &= 1; > - > /* data access */ > #if !defined(CONFIG_USER_ONLY) > /* XXX: put correct access by using cpu_restore_state() > @@ -347,8 +348,6 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int r > int access_type; > int ret = 0; > > - rw &= 1; > - > /* data access */ > access_type = ACCESS_INT; > ret = get_physical_address(env, &physical, &prot,