Re: [PATCH 2/2] mwait_idle: Broadwell support

["Chen, Tiejun" <tiejun.chen@intel.com>]

Did you guys validate this in real machine? Or any potential side affect?

When I do IGD GFX passthrough with qemu-xen-traditional, I found in the 
boot phase of VM, the target will reboot. After I revert this everything 
is fine.

Note I don't add anything into codes. Here I just build Xen unstable 4.5 
to use qemu-xen-traditional. And additionally, my BDW is based on 
stepping E, and guest is WindXP.

Thanks
Tiejun

On 2014/9/8 20:42, Ross Lagerwall wrote:
> From: Len Brown <len.brown@intel.com>
>
> Broadwell (BDW) is similar to Haswell (HSW), the preceding processor generation.
>
> Currently, the only difference in their C-state tables is that PC3 max exit latency
> is 33usec on HSW and 40usec on BDW.
>
> Signed-off-by: Len Brown <len.brown@intel.com>
> Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com>
> ---
>   xen/arch/x86/cpu/mwait-idle.c | 60 +++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 60 insertions(+)
>
> diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
> index 2c5864e..4d5d31d 100644
> --- a/xen/arch/x86/cpu/mwait-idle.c
> +++ b/xen/arch/x86/cpu/mwait-idle.c
> @@ -398,6 +398,58 @@ static const struct cpuidle_state hsw_cstates[] = {
>   	{}
>   };
>
> +static struct cpuidle_state bdw_cstates[] = {
> +	{
> +		.name = "C1-BDW",
> +		.flags = MWAIT2flg(0x00),
> +		.exit_latency = 2,
> +		.target_residency = 2,
> +        },
> +	{
> +		.name = "C1E-BDW",
> +		.flags = MWAIT2flg(0x01),
> +		.exit_latency = 10,
> +		.target_residency = 20,
> +        },
> +	{
> +		.name = "C3-BDW",
> +		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
> +		.exit_latency = 40,
> +		.target_residency = 100,
> +        },
> +	{
> +		.name = "C6-BDW",
> +		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
> +		.exit_latency = 133,
> +		.target_residency = 400,
> +        },
> +	{
> +		.name = "C7s-BDW",
> +		.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
> +		.exit_latency = 166,
> +		.target_residency = 500,
> +        },
> +	{
> +		.name = "C8-BDW",
> +		.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
> +		.exit_latency = 300,
> +		.target_residency = 900,
> +        },
> +	{
> +		.name = "C9-BDW",
> +		.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
> +		.exit_latency = 600,
> +		.target_residency = 1800,
> +        },
> +	{
> +		.name = "C10-BDW",
> +		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
> +		.exit_latency = 2600,
> +		.target_residency = 7700,
> +        },
> +        {}
> +};
> +
>   static const struct cpuidle_state atom_cstates[] = {
>   	{
>   		.name = "C1E-ATM",
> @@ -588,6 +640,11 @@ static const struct idle_cpu idle_cpu_hsw = {
>   	.disable_promotion_to_c1e = 1,
>   };
>
> +static const struct idle_cpu idle_cpu_bdw = {
> +	.state_table = bdw_cstates,
> +	.disable_promotion_to_c1e = 1,
> +};
> +
>   static const struct idle_cpu idle_cpu_avn = {
>   	.state_table = avn_cstates,
>   	.disable_promotion_to_c1e = 1,
> @@ -619,6 +676,9 @@ static struct intel_idle_id {
>   	ICPU(0x45, hsw),
>   	ICPU(0x46, hsw),
>   	ICPU(0x4d, avn),
> +	ICPU(0x3d, bdw),
> +	ICPU(0x4f, bdw),
> +	ICPU(0x56, bdw),
>   	{}
>   };
>
>