From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xem6U-0000Z9-D0 for qemu-devel@nongnu.org; Thu, 16 Oct 2014 10:32:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xem6O-0007kA-0T for qemu-devel@nongnu.org; Thu, 16 Oct 2014 10:32:34 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:16045) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xem6N-0007k1-OA for qemu-devel@nongnu.org; Thu, 16 Oct 2014 10:32:27 -0400 Message-ID: <543FD6F8.1020109@imgtec.com> Date: Thu, 16 Oct 2014 15:32:24 +0100 From: Yongbok Kim MIME-Version: 1.0 References: <1405354795-25884-1-git-send-email-leon.alrae@imgtec.com> <1405354795-25884-2-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1405354795-25884-2-git-send-email-leon.alrae@imgtec.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/6] target-mips: add Config5.SBRI List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae , qemu-devel@nongnu.org Cc: aurelien@aurel32.net Please update message body as it also adds dm{f,t}c0 for config{4,5}. See the comment below. Reviewed-by: Yongbok Kim Regards, Yongbok On 14/07/2014 17:19, Leon Alrae wrote: > SDBBP instruction Reserved Instruction control. The purpose of this field is > to restrict availability of SDBBP to kernel mode operation. > > If the bit is set then SDBBP instruction can only be executed in kernel mode. > User execution of SDBBP will cause a Reserved Instruction exception. > > Signed-off-by: Leon Alrae > --- > target-mips/cpu.h | 11 +++++++++-- > target-mips/translate.c | 24 +++++++++++++++++++++++- > 2 files changed, 32 insertions(+), 3 deletions(-) > > diff --git a/target-mips/cpu.h b/target-mips/cpu.h > index 23bb22c..2a762d2 100644 > --- a/target-mips/cpu.h > +++ b/target-mips/cpu.h > @@ -410,6 +410,7 @@ struct CPUMIPSState { > #define CP0C5_CV 29 > #define CP0C5_EVA 28 > #define CP0C5_MSAEn 27 > +#define CP0C5_SBRI 6 > #define CP0C5_UFR 2 > #define CP0C5_NFExists 0 > int32_t CP0_Config6; > @@ -461,7 +462,7 @@ struct CPUMIPSState { > #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ > uint32_t hflags; /* CPU State */ > /* TMASK defines different execution modes */ > -#define MIPS_HFLAG_TMASK 0xC07FF > +#define MIPS_HFLAG_TMASK 0x2C07FF > #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ > /* The KSU flags must be the lowest bits in hflags. The flag order > must be the same as defined for CP0 Status. This allows to use > @@ -504,6 +505,7 @@ struct CPUMIPSState { > #define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resources. */ > /* Extra flag about HWREna register. */ > #define MIPS_HFLAG_HWRENA_ULR 0x100000 /* ULR bit from HWREna is set. */ > +#define MIPS_HFLAG_SBRI 0x200000 /* R6 SDBBP causes RI excpt. in user mode */ also in supervisor mode. :) > target_ulong btarget; /* Jump / branch target */ > target_ulong bcond; /* Branch condition (if needed) */ > > @@ -759,7 +761,8 @@ static inline void compute_hflags(CPUMIPSState *env) > { > env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | > MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | > - MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2); > + MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | > + MIPS_HFLAG_SBRI); > if (!(env->CP0_Status & (1 << CP0St_EXL)) && > !(env->CP0_Status & (1 << CP0St_ERL)) && > !(env->hflags & MIPS_HFLAG_DM)) { > @@ -795,6 +798,10 @@ static inline void compute_hflags(CPUMIPSState *env) > if (env->CP0_Status & (1 << CP0St_FR)) { > env->hflags |= MIPS_HFLAG_F64; > } > + if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && > + (env->CP0_Config5 & (1 << CP0C5_SBRI))) { > + env->hflags |= MIPS_HFLAG_SBRI; > + } > if (env->insn_flags & ASE_DSPR2) { > /* Enables access MIPS DSP resources, now our cpu is DSP ASER2, > so enable to access DSPR2 resources. */ > diff --git a/target-mips/translate.c b/target-mips/translate.c > index b931574..d0f695a 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -6273,6 +6273,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) > gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); > rn = "Config3"; > break; > + case 4: > + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); > + rn = "Config4"; > + break; > + case 5: > + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); > + rn = "Config5"; > + break; > /* 6,7 are implementation dependent */ > case 6: > gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); > @@ -6891,6 +6899,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) > /* ignored */ > rn = "Config3"; > break; > + case 4: > + /* currently ignored */ > + rn = "Config4"; > + break; > + case 5: > + gen_helper_mtc0_config5(cpu_env, arg); > + rn = "Config5"; > + /* Stop translation as we may have switched the execution mode */ > + ctx->bstate = BS_STOP; > + break; > /* 6,7 are implementation dependent */ > default: > rn = "Invalid config selector"; > @@ -15886,7 +15904,11 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) > } > break; > case R6_OPC_SDBBP: > - generate_exception(ctx, EXCP_DBp); > + if (ctx->hflags & MIPS_HFLAG_SBRI) { > + generate_exception(ctx, EXCP_RI); > + } else { > + generate_exception(ctx, EXCP_DBp); > + } > break; > #if defined(TARGET_MIPS64) > case OPC_DLSA: