All of lore.kernel.org
 help / color / mirror / Atom feed
From: Yongbok Kim <yongbok.kim@imgtec.com>
To: Leon Alrae <leon.alrae@imgtec.com>, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 3/6] target-mips: CP0_Status.CU0 no longer allows the user to access CP0
Date: Fri, 17 Oct 2014 10:58:11 +0100	[thread overview]
Message-ID: <5440E833.1010900@imgtec.com> (raw)
In-Reply-To: <1405354795-25884-4-git-send-email-leon.alrae@imgtec.com>

Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>

Regards,
Yongbok

On 14/07/2014 17:19, Leon Alrae wrote:
> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
> ---
>   target-mips/cpu.h |    3 ++-
>   1 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index a35ab9d..b981ec7 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -789,7 +789,8 @@ static inline void compute_hflags(CPUMIPSState *env)
>           }
>       }
>   #endif
> -    if ((env->CP0_Status & (1 << CP0St_CU0)) ||
> +    if (((env->CP0_Status & (1 << CP0St_CU0)) &&
> +         !(env->insn_flags & ISA_MIPS32R6)) ||
>           !(env->hflags & MIPS_HFLAG_KSU)) {
>           env->hflags |= MIPS_HFLAG_CP0;
>       }

  reply	other threads:[~2014-10-17  9:58 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-14 16:19 [Qemu-devel] [PATCH 0/6] target-mips: implement new MIPS64 Release 6 features Leon Alrae
2014-07-14 16:19 ` [Qemu-devel] [PATCH 1/6] target-mips: add Config5.SBRI Leon Alrae
2014-10-16 14:32   ` Yongbok Kim
2014-07-14 16:19 ` [Qemu-devel] [PATCH 2/6] target-mips: implement forbidden slot Leon Alrae
2014-10-20 11:10   ` Yongbok Kim
2014-07-14 16:19 ` [Qemu-devel] [PATCH 3/6] target-mips: CP0_Status.CU0 no longer allows the user to access CP0 Leon Alrae
2014-10-17  9:58   ` Yongbok Kim [this message]
2014-07-14 16:19 ` [Qemu-devel] [PATCH 4/6] target-mips: add restrictions for possible values in registers Leon Alrae
2014-10-20 10:19   ` Yongbok Kim
2014-10-21 13:54     ` Leon Alrae
2014-07-14 16:19 ` [Qemu-devel] [PATCH 5/6] target-mips: correctly handle access to unimplemented CP0 register Leon Alrae
2014-10-20 10:49   ` Yongbok Kim
2014-07-14 16:19 ` [Qemu-devel] [PATCH 6/6] target-mips: enable features in MIPS64R6-generic CPU Leon Alrae
2014-10-20 14:23   ` Yongbok Kim

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5440E833.1010900@imgtec.com \
    --to=yongbok.kim@imgtec.com \
    --cc=aurelien@aurel32.net \
    --cc=leon.alrae@imgtec.com \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.