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Date: Wed, 22 Oct 2014 12:35:02 +0100
From: James Hogan <james.hogan@imgtec.com>
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Subject: Re: [Qemu-devel] [PATCH 01/20] target-mips: add MSA defines and
 data structure
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To: Yongbok Kim <yongbok.kim@imgtec.com>, qemu-devel@nongnu.org
Cc: cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net

Hi,

On 14/07/14 10:55, Yongbok Kim wrote:
> +union wr_t {
> +    int8_t  b[MSA_WRLEN/8];
> +    int16_t h[MSA_WRLEN/16];
> +    int32_t w[MSA_WRLEN/32];
> +    int64_t d[MSA_WRLEN/64];

This is incorrect on a big endian host. The least significant bits of
the lowest indexed element should always alias.

With a compiler for little endian this will work fine since b[0] will
alias the least significant bits of h[0], w[0], and d[0], whereas with a
compiler for big endian, b[0] will alias the upper byte of h[0], w[0],
and d[0].

> diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
> index 9dfa516..11722bb 100644
> --- a/target-mips/mips-defs.h
> +++ b/target-mips/mips-defs.h
> @@ -41,6 +41,7 @@
>  #define		ASE_MT		0x00020000
>  #define		ASE_SMARTMIPS	0x00040000
>  #define 	ASE_MICROMIPS	0x00080000
> +#define     ASE_MSA     0x00100000

inconsistent whitespace... though maybe it was already incorrect.

Cheers
James