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Date: Wed, 22 Oct 2014 13:18:22 +0100
From: James Hogan <james.hogan@imgtec.com>
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Subject: Re: [Qemu-devel] [PATCH 06/20] target-mips: add MSA opcode enum
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To: Yongbok Kim <yongbok.kim@imgtec.com>, qemu-devel@nongnu.org
Cc: cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net

Hi,

On 14/07/14 10:55, Yongbok Kim wrote:
> @@ -835,6 +839,8 @@ enum {
>      OPC_BC1      = (0x08 << 21) | OPC_CP1, /* bc */
>      OPC_BC1ANY2  = (0x09 << 21) | OPC_CP1,
>      OPC_BC1ANY4  = (0x0A << 21) | OPC_CP1,
> +    OPC_MSA_BZ_V = (0x0B << 21) | OPC_CP1,
> +    OPC_MSA_BNZ_V = (0x0F << 21) | OPC_CP1,

I don't think any of the existing secondary opcodes have the ASE
prefixed, and the instruction mnemonics should already be unique, so is
it worth dropping the MSA_ on these and the other secondary opcodes?

> +    /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
> +    OPC_MSA_FILL_df = (0x00 << 16) | OPC_MSA_2R,
> +    OPC_MSA_PCNT_df = (0x04 << 16) | OPC_MSA_2R,
> +    OPC_MSA_NLOC_df = (0x08 << 16) | OPC_MSA_2R,
> +    OPC_MSA_NLZC_df = (0x0C << 16) | OPC_MSA_2R,

it might be more consistent (and more directly comparable to the
encoding table in the manual) to use a shift of 18 here, kind of like
you did for the I5 instructions.

Same for the 2RF ones below but with a shift of 17.

> +
> +    /* 2RF instruction df(bit 16) = _w, _d */

> +    OPC_MSA_FINT_S_df   = (0x18 << 16) | OPC_MSA_2RF,
> +    OPC_MSA_FINT_U_df   = (0x1A << 16) | OPC_MSA_2RF,

the manual calls these two FTINT rather than FINT

Otherwise
Reviewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James