Re: Load latency sampling on Sandy Bridge

[Manuel Selva <manuel.selva@insa-lyon.fr>]

Yes the problem is there ! Thanks I am not enough "fluent" in kernel 
code to identify this. Here is my dmesg:

perf_event_intel: PEBS disabled due to CPU errata, please upgrade microcode

Does it mean that I must "upgrade my hardware" through the upgrade of 
microcode ? I never did such a thing.

Manu

On 10/29/2014 08:12 PM, Vince Weaver wrote:
> On Wed, 29 Oct 2014, Manuel Selva wrote:
>
>> Yes, perf mem doesn't work on my Sandy Bridge. I should be missing something,
>> maybe a kernel parameter somewhere, or something like that, but I don't know
>> where searching ...
>
> well if you're getting operation not supported you are probably running
> into this chunk of code in arch/x86/kernel/cpu/perf_event.c
>
>
> int x86_pmu_hw_config(struct perf_event *event)
> {
>          if (event->attr.precise_ip) {
>                  int precise = 0;
>
>                  /* Support for constant skid */
>                  if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
>                          precise++;
>
>                          /* Support for IP fixup */
>                          if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
>                                  precise++;
>                  }
>
>                  if (event->attr.precise_ip > precise)
>                          return -EOPNOTSUPP;
>
>
>
> and if you look, pebs_broken can be enabled on Sandybridge CPUs due to
> firmware errata.  Did you check your dmesg for messages starting with
> PEBS?
>
> Vince
>