From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexandre Courbot Subject: Re: [PATCH v4 05/12] memory: Add NVIDIA Tegra memory controller support Date: Thu, 30 Oct 2014 19:22:57 +0900 Message-ID: <54521181.8080005@nvidia.com> References: <1413196434-5292-1-git-send-email-thierry.reding@gmail.com> <1413196434-5292-5-git-send-email-thierry.reding@gmail.com> <54520CFE.9060907@nvidia.com> <5452107D.8080207@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <5452107D.8080207-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: =?windows-1252?Q?Terje_Bergstr=F6m?= , Thierry Reding , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Joerg Roedel , Stephen Warren , Alexandre Courbot , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: iommu@lists.linux-foundation.org On Thu, Oct 30, 2014 at 7:18 PM, Terje Bergstr=F6m =20 wrote: > On 30.10.2014 12:03, Alexandre Courbot wrote: >> I had to change the .reg of TEGRA_SWGROUP_GPU to 0xaac to get the I= OMMU >> to work with GK20A. The reason is still not completely clear to me,= but >> if you look at the TRM you see that 0xaa8 is basically constant, wi= th >> the SMMU translation bit hardcoded to DISABLE (and the ASID field b= eing >> meaningless in that case). However right after that register you ha= ve a >> functional one named GPUB instead of GPU, and this one is fully >> writeable (and has the expected effect). > > GPU has two SW group IDs, because it accesses memory both with and > without translation. The bit 34 in addresses in f.ex. PTE chooses > between the two. Indeed, to enable SMMU translation I have to program 0xaac correctly=20 *and* set the bit 34 of every address that needs to go through the SMMU= =2E > GPU is hard-wired to disable translation. For GPUB translation can b= e > enabled. So should I understand that the GPU group is for addresses without bit=20 34 set (hence forcibly disabled) while GPUB is used when that bit is=20 set? Or is it something else? From mboxrd@z Thu Jan 1 00:00:00 1970 From: acourbot@nvidia.com (Alexandre Courbot) Date: Thu, 30 Oct 2014 19:22:57 +0900 Subject: [PATCH v4 05/12] memory: Add NVIDIA Tegra memory controller support In-Reply-To: <5452107D.8080207@nvidia.com> References: <1413196434-5292-1-git-send-email-thierry.reding@gmail.com> <1413196434-5292-5-git-send-email-thierry.reding@gmail.com> <54520CFE.9060907@nvidia.com> <5452107D.8080207@nvidia.com> Message-ID: <54521181.8080005@nvidia.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Oct 30, 2014 at 7:18 PM, Terje Bergstr?m wrote: > On 30.10.2014 12:03, Alexandre Courbot wrote: >> I had to change the .reg of TEGRA_SWGROUP_GPU to 0xaac to get the IOMMU >> to work with GK20A. The reason is still not completely clear to me, but >> if you look at the TRM you see that 0xaa8 is basically constant, with >> the SMMU translation bit hardcoded to DISABLE (and the ASID field being >> meaningless in that case). However right after that register you have a >> functional one named GPUB instead of GPU, and this one is fully >> writeable (and has the expected effect). > > GPU has two SW group IDs, because it accesses memory both with and > without translation. The bit 34 in addresses in f.ex. PTE chooses > between the two. Indeed, to enable SMMU translation I have to program 0xaac correctly *and* set the bit 34 of every address that needs to go through the SMMU. > GPU is hard-wired to disable translation. For GPUB translation can be > enabled. So should I understand that the GPU group is for addresses without bit 34 set (hence forcibly disabled) while GPUB is used when that bit is set? Or is it something else?