Re: [Qemu-devel] [PATCH v2 5/5] target-tricore: Add instructions of RC opcode format

[Richard Henderson <rth@twiddle.net>]

On 10/30/2014 08:59 AM, Bastian Koppelmann wrote:
> Add instructions of RC opcode format.
> Add helper for mul, sha, absdif with signed saturation on overflow.
> Add helper for add, sub, mul with unsigned saturation on overflow.
> Add microcode generator functions:
>     * gen_add_CC, which calculates the carry bit.
>     * gen_addc_CC, which adds the carry bit to the add and calculates the carry bit.
>     * gen_absdif, which calculates the absolute difference.
>     * gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg.
>     * gen_sh_hi, which shifts two 16bit words in one reg.
>     * gen_sha_hi, which does a arithmetic shift on two 16bit words.
>     * gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb.
>     * gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
>       with the lsb of the result.
>     * gen_eqany_bi/hi, which checks ever byte/hword on equality.
> 
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> v1 -> v2:
>     - gen_sha_hi: Remove mask for low in case shift_count > 0, since deposit handles that.
>     - gen_sha_hi: Remove mask for high in case shift <= 0, since deposit handles that.

Reviewed-by: Richard Henderson <rth@twiddle.net>


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