From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58190) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkeLG-0000BP-Po for qemu-devel@nongnu.org; Sat, 01 Nov 2014 15:28:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XkeLA-0006AU-Gu for qemu-devel@nongnu.org; Sat, 01 Nov 2014 15:28:06 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:60895) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkeLA-0006A7-B3 for qemu-devel@nongnu.org; Sat, 01 Nov 2014 15:28:00 -0400 Message-ID: <54553420.7030508@imgtec.com> Date: Sat, 1 Nov 2014 19:27:28 +0000 From: Leon Alrae MIME-Version: 1.0 References: <1414154549-2102-1-git-send-email-leon.alrae@imgtec.com> <1414154549-2102-9-git-send-email-leon.alrae@imgtec.com> <5450F1EA.3060304@imgtec.com> In-Reply-To: <5450F1EA.3060304@imgtec.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 08/15] target-mips: add BadInstr and BadInstrP support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim Cc: qemu-devel@nongnu.org, aurelien@aurel32.net Hi Yongbok, On 29/10/14 13:55, Yongbok Kim wrote: > On 24/10/2014 13:42, Leon Alrae wrote: >> case EXCP_TLBRI: >> cause = 19; >> + update_badinstr = 1; >> goto set_EPC; >> case EXCP_TLBXI: >> cause = 20; > > TLBXI requires updating the register. TLBXI exception can be generated by instruction fetch or MIPS16 PC-relative load. IIUC if TLBXI is caused by instruction fetch the value stored in BadInstr is unpredictable as valid instruction word is not available (the same case as TLB Refill - Instruction Fetch). Therefore in context of Release 6 the implementation is correct. As far as MIPS16 is concerned, this is similar limitation which we discussed for patch #4 (i.e. MIPS16 PC-relative load should ignore RI bit). Regards, Leon