From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkzM7-0007yX-BG for qemu-devel@nongnu.org; Sun, 02 Nov 2014 12:54:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XkzM2-0000on-8M for qemu-devel@nongnu.org; Sun, 02 Nov 2014 12:54:23 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:39331) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkzM2-0000oh-0M for qemu-devel@nongnu.org; Sun, 02 Nov 2014 12:54:18 -0500 Message-ID: <54566FA8.7090301@imgtec.com> Date: Sun, 2 Nov 2014 17:53:44 +0000 From: Leon Alrae MIME-Version: 1.0 References: <1414819733-30765-1-git-send-email-yongbok.kim@imgtec.com> <1414819733-30765-11-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1414819733-30765-11-git-send-email-yongbok.kim@imgtec.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 10/19] target-mips: add MSA I5 format instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim Cc: qemu-devel@nongnu.org, aurelien@aurel32.net Hi Yongbok, On 01/11/14 05:28, Yongbok Kim wrote: > + TCGv_i32 timm = tcg_temp_new_i32(); > + tcg_gen_movi_i32(timm, u5); > + > + switch (MASK_MSA_I5(ctx->opcode)) { > + case OPC_ADDVI_df: > + gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm); > + break; > + case OPC_SUBVI_df: > + gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); > + break; > + case OPC_MAXI_S_df: > + tcg_gen_movi_i32(timm, s5); > + gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); I think tcg_gen_movi_i32(timm, u5) shouldn't be in front of the switch, this operation is useless for instructions having signed immediate. Probably it's not a big deal as tcg will optimize it out, but it needs to be corrected at some point (the same applies to the 3RF group introduced in patch #14). Otherwise, Reviewed-by: Leon Alrae