diff for duplicates of <5458CE31.3040404@linux.intel.com> diff --git a/a/1.txt b/N1/1.txt index 5715d8b..6583775 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -11,7 +11,7 @@ GIV irqdomain (manage SPIs in GICv2 controller) Regards! Gerry -On 2014/11/4 6:16, suravee.suthikulpanit@amd.com wrote: +On 2014/11/4 6:16, suravee.suthikulpanit at amd.com wrote: > From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > > ARM GICv2m specification extends GICv2 to support MSI(-X) with @@ -74,7 +74,7 @@ On 2014/11/4 6:16, suravee.suthikulpanit@amd.com wrote: > + > +Example: > + -> + interrupt-controller@e1101000 { +> + interrupt-controller at e1101000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <2>; @@ -86,7 +86,7 @@ On 2014/11/4 6:16, suravee.suthikulpanit@amd.com wrote: > + <0x0 0xe112f000 0 0x02000>, > + <0x0 0xe1140000 0 0x10000>, > + <0x0 0xe1160000 0 0x10000>; -> + v2m0: v2m@0x8000 { +> + v2m0: v2m at 0x8000 { > + compatible = "arm,gic-v2m-frame"; > + msi-controller; > + reg = <0x0 0x80000 0 0x1000>; @@ -94,7 +94,7 @@ On 2014/11/4 6:16, suravee.suthikulpanit@amd.com wrote: > + > + .... > + -> + v2mN: v2m@0x9000 { +> + v2mN: v2m at 0x9000 { > + compatible = "arm,gic-v2m-frame"; > + msi-controller; > + reg = <0x0 0x90000 0 0x1000>; diff --git a/a/content_digest b/N1/content_digest index 2b7e4b7..bd3a24f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,22 +1,9 @@ "ref\01415052977-26036-1-git-send-email-suravee.suthikulpanit@amd.com\0" "ref\01415052977-26036-3-git-send-email-suravee.suthikulpanit@amd.com\0" - "From\0Jiang Liu <jiang.liu@linux.intel.com>\0" - "Subject\0Re: [V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)\0" + "From\0jiang.liu@linux.intel.com (Jiang Liu)\0" + "Subject\0[V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)\0" "Date\0Tue, 04 Nov 2014 21:01:37 +0800\0" - "To\0suravee.suthikulpanit@amd.com" - marc.zyngier@arm.com - mark.rutland@arm.com - jason@lakedaemon.net - " tglx@linutronix.de\0" - "Cc\0Catalin.Marinas@arm.com" - Will.Deacon@arm.com - liviu.dudau@arm.com - Harish.Kasiviswanathan@amd.com - linux-arm-kernel@lists.infradead.org - linux-pci@vger.kernel.org - linux-kernel@vger.kernel.org - linux-doc@vger.kernel.org - " devicetree@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Suravee,\n" @@ -32,7 +19,7 @@ "Regards!\n" "Gerry\n" "\n" - "On 2014/11/4 6:16, suravee.suthikulpanit@amd.com wrote:\n" + "On 2014/11/4 6:16, suravee.suthikulpanit at amd.com wrote:\n" "> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>\n" "> \n" "> ARM GICv2m specification extends GICv2 to support MSI(-X) with\n" @@ -95,7 +82,7 @@ "> +\n" "> +Example:\n" "> +\n" - "> +\tinterrupt-controller@e1101000 {\n" + "> +\tinterrupt-controller at e1101000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <2>;\n" @@ -107,7 +94,7 @@ "> +\t\t <0x0 0xe112f000 0 0x02000>,\n" "> +\t\t <0x0 0xe1140000 0 0x10000>,\n" "> +\t\t <0x0 0xe1160000 0 0x10000>;\n" - "> +\t\tv2m0: v2m@0x8000 {\n" + "> +\t\tv2m0: v2m at 0x8000 {\n" "> +\t\t\tcompatible = \"arm,gic-v2m-frame\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\treg = <0x0 0x80000 0 0x1000>;\n" @@ -115,7 +102,7 @@ "> +\n" "> +\t\t....\n" "> +\n" - "> +\t\tv2mN: v2m@0x9000 {\n" + "> +\t\tv2mN: v2m at 0x9000 {\n" "> +\t\t\tcompatible = \"arm,gic-v2m-frame\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\treg = <0x0 0x90000 0 0x1000>;\n" @@ -569,4 +556,4 @@ "> }\n" > -3d4a2671efa8251751fcb5f0afdd01baa452ea86f2f8fce893f94b04648e3f94 +e1b0cd991c3a3c8267d5fecb4d2671dab3784d43105e9856d5deec2411ae7631
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