Re: [Qemu-devel] [PATCH 2/7] target-ppc: Introduce gen_set_cr1_from_fpscr

[Tom Musta <tommusta@gmail.com>]

On 11/4/2014 9:58 AM, Paolo Bonzini wrote:
> What tree are these patches based on?  Alex's tree already has a
> 
> commit 15a6b218c221a34b12e81790f427efec3108dce9
> Author: Paolo Bonzini <pbonzini@redhat.com>
> Date:   Thu Aug 28 19:15:07 2014 +0200
> 
>     ppc: rename gen_set_cr6_from_fpscr
> 
>     It sets CR1, not CR6 (and the spec agrees).
> 
>     Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>     Reviewed-by: Tom Musta <tommusta@gmail.com>
>     Tested-by: Tom Musta <tommusta@gmail.com>
>     Signed-off-by: Alexander Graf <agraf@suse.de>
> 
> that conflicts (semantically) with this.
> 
> Paolo

Ahhh .. I had forgotten about that one.  My patches are based on master.

I will rebase on ppc-next and submit V2.

> 
> On 03/11/2014 21:01, Tom Musta wrote:
>> The Power ISA supports a mode in many floating point instructions whereby
>> the Condition Register field 1 (CR[1]) receives a copy of the Floating
>> Point Status (FPSCR) bits 32:35, also known as FX, FEX VX and OX.
>>
>> The existing QEMU code is mostly wrong -- CR[1] is set to the Floating
>> Point Condition Code (FPSCR[FPCC]).  Furthermore, this code is buried
>> inside the code that generates the FPSCR[FPRF] code, which is awkward.
>>
>> Introduce a new generator utility that correctly sets CR[1] from the
>> FPSCR bits.  Subsequent patches will correct various segments of
>> the defective code and will clean up the gen_compute_fprf()
>> utility.
>>
>> Signed-off-by: Tom Musta <tommusta@gmail.com>
>> ---
>>  target-ppc/translate.c |    8 ++++++++
>>  1 files changed, 8 insertions(+), 0 deletions(-)
>>
>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
>> index d03daea..7775bf4 100644
>> --- a/target-ppc/translate.c
>> +++ b/target-ppc/translate.c
>> @@ -249,6 +249,14 @@ static inline void gen_reset_fpstatus(void)
>>      gen_helper_reset_fpstatus(cpu_env);
>>  }
>>  
>> +static inline void gen_set_cr1_from_fpscr(void)
>> +{
>> +    TCGv_i32 t0 = tcg_temp_new_i32();
>> +    tcg_gen_trunc_tl_i32(t0, cpu_fpscr);
>> +    tcg_gen_shri_i32(cpu_crf[1], t0, 28);
>> +    tcg_temp_free_i32(t0);
>> +}
>> +
>>  static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
>>  {
>>      TCGv_i32 t0 = tcg_temp_new_i32();
>>