From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gyumin Subject: Intel 82599 tx_conf setting Date: Wed, 05 Nov 2014 09:43:43 +0900 Message-ID: <545972BF.9080100@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit To: dev-VfR2kkLFssw@public.gmane.org Return-path: List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" Hi I've read the Intel 82599 official manual and I found that optimal PTHRESH is the tx descriptor buffer size - N (N is CPU cache line divided by 16). 1. I guess the size of the tx descriptor buffer is 128. Isn't it right? Where is the size of the tx descriptor buffer in the official manual? 2. What it means that the TX_PTHRESH=36 in the testpmd.c? If the size of tx descriptor buffer is 128 then optimal thresholds to minimize latency are pthresh=4(cache line / 16), hthresh=0 and wthresh=0. Is there something I missed? Thanks.