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Date: Wed, 5 Nov 2014 15:25:21 +0000
From: Leon Alrae <leon.alrae@imgtec.com>
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Subject: Re: [Qemu-devel] [PATCH] mips: Make CP0.Config4 and CP0.Config5
	registers signed
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To: "Maciej W. Rozycki" <macro@codesourcery.com>, qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>

On 04/11/2014 15:37, Maciej W. Rozycki wrote:
> Make the data type used for the CP0.Config4 and CP0.Config5 registers 
> and their mask signed, for consistency with the remaining 32-bit CP0 
> registers, like CP0.Config0, etc.
> 
> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
> ---
> qemu-mips-config-int32_t.diff
> Index: qemu-git-trunk/target-mips/cpu.h
> ===================================================================
> --- qemu-git-trunk.orig/target-mips/cpu.h	2014-11-02 01:05:19.000000000 +0000
> +++ qemu-git-trunk/target-mips/cpu.h	2014-11-02 01:08:26.527563002 +0000
> @@ -372,11 +372,11 @@ struct CPUMIPSState {
>  #define CP0C3_MT   2
>  #define CP0C3_SM   1
>  #define CP0C3_TL   0
> -    uint32_t CP0_Config4;
> -    uint32_t CP0_Config4_rw_bitmask;
> +    int32_t CP0_Config4;
> +    int32_t CP0_Config4_rw_bitmask;
>  #define CP0C4_M    31
> -    uint32_t CP0_Config5;
> -    uint32_t CP0_Config5_rw_bitmask;
> +    int32_t CP0_Config5;
> +    int32_t CP0_Config5_rw_bitmask;
>  #define CP0C5_M          31
>  #define CP0C5_K          30
>  #define CP0C5_CV         29
> 

Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>