diff for duplicates of <545F05F0.3000702@broadcom.com>

diff --git a/a/1.txt b/N1/1.txt
index 2553162..7760d74 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -169,7 +169,7 @@ dual license?  If it is BSD that should serve both purposes?
 >> +               #address-cells = <1>;
 >> +               #size-cells = <0>;
 >> +
->> +               cpu at 0 {
+>> +               cpu@0 {
 >> +                       device_type = "cpu";
 >> +                       compatible = "arm,cortex-a9";
 >> +                       next-level-cache = <&L2>;
@@ -186,7 +186,7 @@ dual license?  If it is BSD that should serve both purposes?
 >> +               interrupt-parent = <&gic>;
 >> +               ranges;
 >> +
->> +               wdt at 18009000 {
+>> +               wdt@18009000 {
 >> +                        compatible = "arm,sp805" , "arm,primecell";
 >> +                        reg = <0x18009000 0x1000>;
 >> +                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
@@ -195,7 +195,7 @@ dual license?  If it is BSD that should serve both purposes?
 >> +               };
 >> +       };
 >> +
->> +       uart3: serial at 18023000 {
+>> +       uart3: serial@18023000 {
 >> +               compatible = "snps,dw-apb-uart";
 >> +               reg = <0x18023000 0x100>;
 >> +               reg-shift = <2>;
@@ -217,7 +217,7 @@ dual license?  If it is BSD that should serve both purposes?
 >
 >> +       };
 >> +
->> +       uart0: serial at 18020000 {
+>> +       uart0: serial@18020000 {
 >
 > These are also out of order, uart3 is before uart0 (and the registers
 > are in reverse order).
@@ -236,7 +236,7 @@ dual license?  If it is BSD that should serve both purposes?
 >> +               status = "okay";
 >> +       };
 >> +
->> +       gic: interrupt-controller at 19021000 {
+>> +       gic: interrupt-controller@19021000 {
 >> +               compatible = "arm,cortex-a9-gic";
 >> +               #interrupt-cells = <3>;
 >> +               #address-cells = <0>;
@@ -247,7 +247,7 @@ dual license?  If it is BSD that should serve both purposes?
 >> +
 >> +       L2: l2-cache {
 >
-> l2-cache at 19022000
+> l2-cache@19022000
 >
 >> +               compatible = "arm,pl310-cache";
 >> +               reg = <0x19022000 0x1000>;
@@ -255,7 +255,7 @@ dual license?  If it is BSD that should serve both purposes?
 >> +               cache-level = <2>;
 >> +       };
 >> +
->> +       timer at 19020200 {
+>> +       timer@19020200 {
 >> +               compatible = "arm,cortex-a9-global-timer";
 >> +               reg = <0x19020200 0x100>;
 >> +               interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
@@ -383,5 +383,5 @@ dual license?  If it is BSD that should serve both purposes?
 >>
 >> _______________________________________________
 >> linux-arm-kernel mailing list
->> linux-arm-kernel at lists.infradead.org
+>> linux-arm-kernel@lists.infradead.org
 >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/a/content_digest b/N1/content_digest
index ac34240..f273c30 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,10 +1,31 @@
  "ref\01414525992-3678-1-git-send-email-sbranden@broadcom.com\0"
  "ref\01414525992-3678-5-git-send-email-sbranden@broadcom.com\0"
  "ref\0CAOesGMjUE-Z3L=FU1nspv5M52UhhJ9-dBLr40RTCz2WEhEPHLA@mail.gmail.com\0"
- "From\0sbranden@broadcom.com (Scott Branden)\0"
- "Subject\0[PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC\0"
+ "From\0Scott Branden <sbranden@broadcom.com>\0"
+ "Subject\0Re: [PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC\0"
  "Date\0Sat, 8 Nov 2014 22:13:04 -0800\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Olof Johansson <olof@lixom.net>\0"
+ "Cc\0Christian Daudt <bcm@fixthebug.org>"
+  Matt Porter <mporter@linaro.org>
+  Russell King <linux@arm.linux.org.uk>
+  Broadcom Kernel Feedback List <bcm-kernel-feedback-list@broadcom.com>
+  Mike Turquette <mturquette@linaro.org>
+  Alex Elder <elder@linaro.org>
+  Rob Herring <robh+dt@kernel.org>
+  Pawel Moll <pawel.moll@arm.com>
+  Mark Rutland <mark.rutland@arm.com>
+  Ian Campbell <ijc+devicetree@hellion.org.uk>
+  Kumar Gala <galak@codeaurora.org>
+  Andrew Morton <akpm@linux-foundation.org>
+  David S. Miller <davem@davemloft.net>
+  Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+  Joe Perches <joe@perches.com>
+  Mauro Carvalho Chehab <m.chehab@samsung.com>
+  Antti Palosaari <crope@iki.fi>
+  devicetree@vger.kernel.org <devicetree@vger.kernel.org>
+  Ray Jui <rjui@broadcom.com>
+  linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>
+ " JD Zheng <jdzheng@broadcom.com>linux\0"
  "\00:1\0"
  "b\0"
  "On 14-11-08 04:22 PM, Olof Johansson wrote:\n"
@@ -178,7 +199,7 @@
  ">> +               #address-cells = <1>;\n"
  ">> +               #size-cells = <0>;\n"
  ">> +\n"
- ">> +               cpu at 0 {\n"
+ ">> +               cpu@0 {\n"
  ">> +                       device_type = \"cpu\";\n"
  ">> +                       compatible = \"arm,cortex-a9\";\n"
  ">> +                       next-level-cache = <&L2>;\n"
@@ -195,7 +216,7 @@
  ">> +               interrupt-parent = <&gic>;\n"
  ">> +               ranges;\n"
  ">> +\n"
- ">> +               wdt at 18009000 {\n"
+ ">> +               wdt@18009000 {\n"
  ">> +                        compatible = \"arm,sp805\" , \"arm,primecell\";\n"
  ">> +                        reg = <0x18009000 0x1000>;\n"
  ">> +                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -204,7 +225,7 @@
  ">> +               };\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       uart3: serial at 18023000 {\n"
+ ">> +       uart3: serial@18023000 {\n"
  ">> +               compatible = \"snps,dw-apb-uart\";\n"
  ">> +               reg = <0x18023000 0x100>;\n"
  ">> +               reg-shift = <2>;\n"
@@ -226,7 +247,7 @@
  ">\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       uart0: serial at 18020000 {\n"
+ ">> +       uart0: serial@18020000 {\n"
  ">\n"
  "> These are also out of order, uart3 is before uart0 (and the registers\n"
  "> are in reverse order).\n"
@@ -245,7 +266,7 @@
  ">> +               status = \"okay\";\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       gic: interrupt-controller at 19021000 {\n"
+ ">> +       gic: interrupt-controller@19021000 {\n"
  ">> +               compatible = \"arm,cortex-a9-gic\";\n"
  ">> +               #interrupt-cells = <3>;\n"
  ">> +               #address-cells = <0>;\n"
@@ -256,7 +277,7 @@
  ">> +\n"
  ">> +       L2: l2-cache {\n"
  ">\n"
- "> l2-cache at 19022000\n"
+ "> l2-cache@19022000\n"
  ">\n"
  ">> +               compatible = \"arm,pl310-cache\";\n"
  ">> +               reg = <0x19022000 0x1000>;\n"
@@ -264,7 +285,7 @@
  ">> +               cache-level = <2>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       timer at 19020200 {\n"
+ ">> +       timer@19020200 {\n"
  ">> +               compatible = \"arm,cortex-a9-global-timer\";\n"
  ">> +               reg = <0x19020200 0x100>;\n"
  ">> +               interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -392,7 +413,7 @@
  ">>\n"
  ">> _______________________________________________\n"
  ">> linux-arm-kernel mailing list\n"
- ">> linux-arm-kernel at lists.infradead.org\n"
+ ">> linux-arm-kernel@lists.infradead.org\n"
  >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 
-bec29c6b015499640a3376f862bced7fac6dc4480daca773da40deb9bea4227e
+410eee67ae1355a5c1d8b6a1af9ffc526efd14d087d30f1cf2bacb34fe5b8c4a
