Re: PCI passthrough (pci-attach) to HVM guests bug (BAR64 addresses are bogus)

[Malcolm Crossley <malcolm.crossley@citrix.com>]

On 12/11/14 10:11, Jan Beulich wrote:
>>>> On 12.11.14 at 11:01, <malcolm.crossley@citrix.com> wrote:
>> As for the CRS regions: These typically describe the BIOS set limits in
>> hardware configuration for the MMIO hole itself. On single socket
>> systems anything which isn't RAM or another predefined region decodes to
>> MMIO. This is probably why Jan's Dell system has a CRS region which
>> covers the entire address space.
>>
>> On multi socket systems the CRS is very important because the chipset is
>> configured to only decode certain regions to the PCI express ports, if
>> you use an address out side of those regions then accessing that address
>> will go "nowhere" and the machine will crash.
> 
> Don't you mean multi-node instead of multi-socket here? Since what
> matters is how the I/O subsystem is organized; the CPU topology is
> pretty uninteresting for this.
> 

Yes, multi-IO-node would be the correct description (I used socket
because most people would understand that more clearly). I don't like
using the term "node" on it's own because IO and memory node's can be
quite different. The specific hardware dictating the address space
partitioning is the coherency fabric (QPI links/HT links).

Malcolm

> Jan
>