From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg
Date: Fri, 14 Nov 2014 13:27:26 -0800 [thread overview]
Message-ID: <546673BE.4020801@freescale.com> (raw)
In-Reply-To: <1410949674-15633-1-git-send-email-Priyanka.Jain@freescale.com>
On 09/17/2014 03:27 AM, Priyanka Jain wrote:
> -A_007662 states that for x1 link width, PCIe2 controller trains in
> Gen1 speed while configured for Gen2 speed.
> Workaround:Set the width to x1 and speed to Gen2 by writing to
> CCSR registers in PBI phase
>
> -A_008007 states that PVR register may show random value.
> Workaround: Reset PVR register using DCSR space in PBI phase
>
> Add PBI based software workaround for A_007662 and A_008007
> in t104x_pbi.cfg. This is required for SPL-based bootloaders
> like NAND-boot, SD-boot, SPI-boot
>
> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
> ---
Applied to u-boot-mpc85xx master. Thanks.
York
prev parent reply other threads:[~2014-11-14 21:27 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-17 10:27 [U-Boot] [PATCH] t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg Priyanka Jain
2014-11-14 21:27 ` York Sun [this message]
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