From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mout.kundenserver.de ([212.227.17.10]:61807 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757246AbaGRTuU (ORCPT ); Fri, 18 Jul 2014 15:50:20 -0400 From: Arnd Bergmann To: Rob Herring Cc: Murali Karicheri , "linux-arm-kernel@lists.infradead.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Russell King , Grant Likely , Rob Herring , Mohit Kumar , Jingoo Han , Bjorn Helgaas , Pratyush Anand , Richard Zhu , Kishon Vijay Abraham I , Marek Vasut , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy Dunlap Subject: Re: [PATCH v6 4/5] PCI: add PCI controller for keystone PCIe h/w Date: Fri, 18 Jul 2014 21:50:08 +0200 Message-ID: <5467203.eMVRoNeSx1@wuerfel> In-Reply-To: References: <1405696469-7172-1-git-send-email-m-karicheri2@ti.com> <1405696469-7172-5-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Sender: linux-pci-owner@vger.kernel.org List-ID: On Friday 18 July 2014 14:31:39 Rob Herring wrote: > > + > > + Example: > > + pcie_msi_intc: msi-interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + interrupt-parent = <&gic>; > > + interrupts = , > > + , > > + , > > + , > > + , > > + , > > + , > > + ; > > + }; > > + > > +pcie_intc: Interrupt controller device node for Legacy irq chip > > + interrupt-cells: should be set to 1 > > + interrupt-parent: Parent interrupt controller phandle > > + interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines > > + > > + Example: > > + pcie_intc: legacy-interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + interrupt-parent = <&gic>; > > + interrupts = , > > + , > > + , > > + ; > > + }; > > This seems wrong. Legacy interrupts should be described with > interrupt-map and then PCI child devices have a standard interrupt > specifier. > > I'm not sure about MSIs, but I would think they would have a standard > format too. > IIRC, it's actually the correct way to do this here: the problem is that the PCI IRQs are not directly connected to the GIC, but instead there is a nested irqchip that has each PCI IRQ routed to it and that requires an extra EOI for each interrupt. The interrupt-map in the PCI host points to this special irqchip rather than to the GIC. Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: arnd@arndb.de (Arnd Bergmann) Date: Fri, 18 Jul 2014 21:50:08 +0200 Subject: [PATCH v6 4/5] PCI: add PCI controller for keystone PCIe h/w In-Reply-To: References: <1405696469-7172-1-git-send-email-m-karicheri2@ti.com> <1405696469-7172-5-git-send-email-m-karicheri2@ti.com> Message-ID: <5467203.eMVRoNeSx1@wuerfel> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Friday 18 July 2014 14:31:39 Rob Herring wrote: > > + > > + Example: > > + pcie_msi_intc: msi-interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + interrupt-parent = <&gic>; > > + interrupts = , > > + , > > + , > > + , > > + , > > + , > > + , > > + ; > > + }; > > + > > +pcie_intc: Interrupt controller device node for Legacy irq chip > > + interrupt-cells: should be set to 1 > > + interrupt-parent: Parent interrupt controller phandle > > + interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines > > + > > + Example: > > + pcie_intc: legacy-interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + interrupt-parent = <&gic>; > > + interrupts = , > > + , > > + , > > + ; > > + }; > > This seems wrong. Legacy interrupts should be described with > interrupt-map and then PCI child devices have a standard interrupt > specifier. > > I'm not sure about MSIs, but I would think they would have a standard > format too. > IIRC, it's actually the correct way to do this here: the problem is that the PCI IRQs are not directly connected to the GIC, but instead there is a nested irqchip that has each PCI IRQ routed to it and that requires an extra EOI for each interrupt. The interrupt-map in the PCI host points to this special irqchip rather than to the GIC. Arnd