From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yerden Zhumabekov Subject: Re: [PATCH v4 3/5] hash: add fallback to software CRC32 implementation Date: Wed, 19 Nov 2014 10:07:23 +0600 Message-ID: <546C177B.10003@sts.kz> References: <1409724351-23786-1-git-send-email-e_zhumabekov@sts.kz> <20141118144138.GB32375@hmsreliant.think-freely.org> <546B607B.9030808@sts.kz> <20141118160005.GC32375@hmsreliant.think-freely.org>, <546B7E2D.7050705@sts.kz> <12C2AAD9525203489F7B523D670129D91CCF3615@ex10-mbx-31007.ant.amazon.com> Mime-Version: 1.0 Content-Type: text/plain; charset="koi8-r" Content-Transfer-Encoding: quoted-printable To: "Wang, Shawn" , "dev-VfR2kkLFssw@public.gmane.org" Return-path: In-Reply-To: <12C2AAD9525203489F7B523D670129D91CCF3615-CFWIZfY9kHm7lkz2zA3lWedPMyk3kRfBmjCW/i4Lttk@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" 18.11.2014 23:29, Wang, Shawn =D0=C9=DB=C5=D4: > I have a general question about using CPUID to detect supported instruc= tion set. > What if we are compiling the software with some old hardware which does= not support SSE4.2, but run it on new hardware which does support SSE4.2= =2E Is there still a static way to force the compiler to turn on the SSE4= =2E2 support?=20 > I guess for SSE4.2, most of the CPU has support for it now. But for AVX= 2, this might not be the case. According to gcc 4.7 changes (https://gcc.gnu.org/gcc-4.7/changes.html) they've added support for AVX2 instructions since that version. Use -mavx2 or -march=3Dcore-avx2. The latter seems to be supported by ICC= as well, according to Google :) --=20 Sincerely, Yerden Zhumabekov State Technical Service Astana, KZ