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From: Alexander Graf <agraf@suse.de>
To: Tom Musta <tommusta@gmail.com>,
	qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [2.3 V2 PATCH 2/6] target-ppc: Fix Floating Point Move Instructions That Set CR1
Date: Thu, 20 Nov 2014 15:14:09 +0100	[thread overview]
Message-ID: <546DF731.2060303@suse.de> (raw)
In-Reply-To: <1415828764-10582-3-git-send-email-tommusta@gmail.com>



On 12.11.14 22:46, Tom Musta wrote:
> The Floating Point Move instructions (fmr., fabs., fnabs., fneg.,
> and fcpsgn.) incorrectly copy FPSCR[FPCC] instead of [FX,FEX,VX,OX].
> Furthermore, the current code does this via a call to gen_compute_fprf,
> which is awkward since these instructions do not actually set FPRF.
> 
> Change the code to use the gen_set_cr1_from_fpscr utility.
> 
> Signed-off-by: Tom Musta <tommusta@gmail.com>
> ---
>  target-ppc/translate.c |   50 ++++++++++++++++++++++++++++-------------------
>  1 files changed, 30 insertions(+), 20 deletions(-)
> 
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 910ce56..2d79e39 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -2077,6 +2077,21 @@ static void gen_srd(DisasContext *ctx)
>  }
>  #endif
>  
> +#if defined(TARGET_PPC64)
> +static void gen_set_cr1_from_fpscr(DisasContext *ctx)
> +{
> +    TCGv_i32 tmp = tcg_temp_new_i32();
> +    tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
> +    tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
> +    tcg_temp_free_i32(tmp);
> +}
> +#else
> +static void gen_set_cr1_from_fpscr(DisasContext *ctx)
> +{
> +        tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
> +}
> +#endif
> +
>  /***                       Floating-Point arithmetic                       ***/
>  #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
>  static void gen_f##name(DisasContext *ctx)                                    \
> @@ -2370,7 +2385,9 @@ static void gen_fabs(DisasContext *ctx)
>      }
>      tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
>                       ~(1ULL << 63));
> -    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
> +    if (unlikely(Rc(ctx->opcode))) {
> +        gen_set_cr1_from_fpscr(ctx);
> +    }

I don't quite understand this. We set cr1 based on fpscr, but we don't
recalculate the respective fpscr bits?

Wouldn't we get outdated comparison data?


Alex

  reply	other threads:[~2014-11-20 14:14 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-12 21:45 [Qemu-devel] [2.3 V2 PATCH 0/6] target-ppc: Assorted Floating Point Bugs and Cleanup Tom Musta
2014-11-12 21:45 ` [Qemu-devel] [2.3 V2 PATCH 1/6] target-ppc: VXSQRT Should Not Be Set for NaNs Tom Musta
2014-11-12 21:46 ` [Qemu-devel] [2.3 V2 PATCH 2/6] target-ppc: Fix Floating Point Move Instructions That Set CR1 Tom Musta
2014-11-20 14:14   ` Alexander Graf [this message]
2014-11-20 14:32     ` Tom Musta
2014-11-20 14:49       ` Alexander Graf
2014-11-12 21:46 ` [Qemu-devel] [2.3 V2 PATCH 3/6] target-ppc: mffs. Should Set CR1 from FPSCR Bits Tom Musta
2014-11-12 21:46 ` [Qemu-devel] [2.3 V2 PATCH 4/6] target-ppc: Fully Migrate to gen_set_cr1_from_fpscr Tom Musta
2014-11-12 21:46 ` [Qemu-devel] [2.3 V2 PATCH 5/6] target-ppc: Eliminate set_fprf Argument From gen_compute_fprf Tom Musta
2014-11-12 21:46 ` [Qemu-devel] [2.3 V2 PATCH 6/6] target-ppc: Eliminate set_fprf Argument From helper_compute_fprf Tom Musta
2014-11-20 14:51 ` [Qemu-devel] [2.3 V2 PATCH 0/6] target-ppc: Assorted Floating Point Bugs and Cleanup Alexander Graf

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