From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A141CCD54B5 for ; Tue, 19 Sep 2023 11:27:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qiYsu-0001Fv-UF; Tue, 19 Sep 2023 07:27:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qiYss-0001Ey-Iw; Tue, 19 Sep 2023 07:27:14 -0400 Received: from out30-111.freemail.mail.aliyun.com ([115.124.30.111]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qiYsq-0000m5-P5; Tue, 19 Sep 2023 07:27:14 -0400 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R191e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045176; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0VsRHrJV_1695122825; Received: from 30.221.108.237(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VsRHrJV_1695122825) by smtp.aliyun-inc.com; Tue, 19 Sep 2023 19:27:06 +0800 Message-ID: <546bc21e-bef7-5a2b-0b03-b3603ba9fb5d@linux.alibaba.com> Date: Tue, 19 Sep 2023 19:26:15 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v2 09/19] target/riscv: make riscv_add_satp_mode_properties() public Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org References: <20230906091647.1667171-1-dbarboza@ventanamicro.com> <20230906091647.1667171-10-dbarboza@ventanamicro.com> From: LIU Zhiwei In-Reply-To: <20230906091647.1667171-10-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=115.124.30.111; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-111.freemail.mail.aliyun.com X-Spam_score_int: -113 X-Spam_score: -11.4 X-Spam_bar: ----------- X-Spam_report: (-11.4 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, NICE_REPLY_A=-1.473, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 2023/9/6 17:16, Daniel Henrique Barboza wrote: > This function is used for both accelerators. Make it public, and call it > from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to > split KVM specific code for the KVM accelerator class in the next patch. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Zhiwei > --- > target/riscv/cpu.c | 5 ++--- > target/riscv/cpu.h | 1 + > target/riscv/kvm.c | 1 + > 3 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0dc9b3201d..50be127f36 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1115,7 +1115,7 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > satp_map->init |= 1 << satp; > } > > -static void riscv_add_satp_mode_properties(Object *obj) > +void riscv_add_satp_mode_properties(Object *obj) > { > RISCVCPU *cpu = RISCV_CPU(obj); > > @@ -1589,12 +1589,11 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj, > static void riscv_cpu_add_user_properties(Object *obj) > { > #ifndef CONFIG_USER_ONLY > - riscv_add_satp_mode_properties(obj); > - > if (kvm_enabled()) { > kvm_riscv_cpu_add_kvm_properties(obj); > return; > } > + riscv_add_satp_mode_properties(obj); > #endif > > riscv_cpu_add_misa_properties(obj); > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b9c4bea3f7..950c2301f2 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -726,6 +726,7 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; > extern Property riscv_cpu_options[]; > > void riscv_cpu_add_misa_properties(Object *cpu_obj); > +void riscv_add_satp_mode_properties(Object *obj); > > /* CSR function table */ > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 7dac01374f..ef6b2cfffe 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -1279,6 +1279,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) > DeviceState *dev = DEVICE(obj); > > riscv_init_user_properties(obj); > + riscv_add_satp_mode_properties(obj); > riscv_cpu_add_misa_properties(obj); > > riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);