Re: [XEN][PATCH] x86/hvm: vlapic: fix RO bits emulation in LVTx regs

[Jan Beulich <jbeulich@suse.com>]

On 26.09.2025 13:34, Grygorii Strashko wrote:
> On 26.09.25 13:52, Jan Beulich wrote:
>> On 26.09.2025 12:38, Grygorii Strashko wrote:
>>> On 26.09.25 11:17, Jan Beulich wrote:
>>>> On 25.09.2025 21:55, Grygorii Strashko wrote:
>>>> While looking at this, don't we have an issue with CMCI as well?
>>>
>>> I see no APIC_CMCI write emulation. only read.
>>
>> guest_wrmsr_x2apic() has
>>
>>      case APIC_CMCI:
> 
> it will end up calling vlapic_reg_write() which doesn't have case statement for
> APIC_CMCI - write ignored.

Which again is what I had described.

>>>> guest_{rd,wr}msr_x2apic() handle it, but vlapic_reg_write() doesn't. I.e. on
>>>> AMD we would fail to deliver #GP when the guest accesses it, while on Intel
>>>> we would lose the value written. And we also don't set its mask bit in
>>>> vlapic_do_init(). I guess I need to make a patch ...
>>>
>>> Is'n it depends on CMCI capability exposing to guest?
>>
>> Yes, that's part of what I was (effectively) saying.
>>
>>> (have no idea what's CMCI :)
>>
>> Corrected Machine Check Interrupt.
> 
> Looking at:
> 
>   #define VLAPIC_VERSION                  0x00050014
> 
> which means "Max LVT Entries" = 6 (5+1)
> 
> Looking at linux kernel apic.c:
> #ifdef CONFIG_X86_MCE_INTEL
> 	if (maxlvt >= 6) {
> 		v = apic_read(APIC_LVTCMCI);
> 		if (!(v & APIC_LVT_MASKED))
> 			apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
> 	}
> #endif
> 
> Which means Xen never really emulated APIC_CMCI, so wouldn't it be correct to just drop APIC_CMCI?

From the SDM it's not quite clear to me whether using the LVT count is the
correct / only way to determine whether there's a CMCI LVT entry. To me
it reads more like the MCG_CAP bit is what is the basis. Perhaps based on
that we should conditionally set the LVT count to 6 (AMD) or 7 (Intel).

> Also, taking into account that it's Intel specific.

Another part of what I said I think needs correcting.

Jan