From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [question] lots of interrupts injected to vm when pressing some key w/o releasing Date: Tue, 25 Nov 2014 10:49:40 +0100 Message-ID: <547450B4.6010909@redhat.com> References: <201411201020560455720@sangfor.com> <546FBD47.3070703@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Cc: Alex Williamson , Xiao Guangrong , "Michael S.Tsirkin" , Gleb Natapov To: "Zhang, Yang Z" , Zhang Haoyu , kvm Return-path: Received: from mx1.redhat.com ([209.132.183.28]:35863 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750802AbaKYJuA (ORCPT ); Tue, 25 Nov 2014 04:50:00 -0500 In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: On 25/11/2014 04:15, Zhang, Yang Z wrote: > > The IRR register means an interrupt was received and not serviced yet, > > similar to the LAPIC or PIC register. It is not the same thing as the > > interrupt line level (it happens to be for level-triggered interrupts). > > Yes, but commit(0bc830b05) changes the behavior: before it , > ioapic->irr is cleared only when userspace lower the irq level. With it, > it is cleared after the edge interrupt is serviced by ioapic. As you > mentioned below, if QEMU tried to set a line twice, than there will be > two interrupts for guest which only one interrupt before commit(0bc830b05). Indeed, but that shouldn't happen. It would be a QEMU bug, since the all-QEMU implementation of the ioapic is doing the same as commit 0bc830b05. Paolo