Re: [PATCH v3 1/2] CPPC as a PID controller backend

[Dirk Brandewie <dirk.brandewie@gmail.com>]

On 11/30/2014 10:26 PM, Viresh Kumar wrote:
> On 1 December 2014 at 11:53, Ashwin Chaugule <ashwin.chaugule@linaro.org> wrote:
>> On 19 November 2014 at 15:36, Ashwin Chaugule
>> <ashwin.chaugule@linaro.org> wrote:
>>> CPPC (Collaborative Processor Performance Control) is defined
>>> in the ACPI 5.0+ spec. It is a method for controlling CPU
>>> performance on a continuous scale using performance feedback
>>> registers. In contrast to the legacy "pstate" scale which is
>>> discretized, and tied to CPU frequency, CPPC works off of an
>>> abstract continuous scale. This lets the platforms freely interpret
>>> the abstract unit and optimize it for power and performance given
>>> its knowledge of thermal budgets and other constraints.
>>>
>>> The PID governor operates on similar concepts and can use CPPC
>>> semantics to acquire the information it needs. This information
>>> may be provided by various platforms via MSRs, CP15s or memory
>>> mapped registers. CPPC helps to wrap all these variations into a
>>> common framework.
>>>
>>> This patch introduces CPPC using PID as its governor for CPU
>>> performance management.
>>>
>>> Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org>
>>> ---
>>>   drivers/cpufreq/Kconfig    |   12 +
>>>   drivers/cpufreq/Makefile   |    1 +
>>>   drivers/cpufreq/acpi_pid.c | 1156 ++++++++++++++++++++++++++++++++++++++++++++
>>>   3 files changed, 1169 insertions(+)
>>>   create mode 100644 drivers/cpufreq/acpi_pid.c
>>
>>
>> Ping.
>>
>> Any comments on these patches?
>
> Redirecting the Ping to Rafael/Dirk :)
>
Ashwin has incorporated my feedback.  I have no issues

--Dirk