From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xvl4M-0002lb-Ab for qemu-devel@nongnu.org; Tue, 02 Dec 2014 05:52:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xvl4H-000747-8Q for qemu-devel@nongnu.org; Tue, 02 Dec 2014 05:52:34 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:53793) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xvl4H-00072V-2l for qemu-devel@nongnu.org; Tue, 02 Dec 2014 05:52:29 -0500 Message-ID: <547D99EB.5040500@imgtec.com> Date: Tue, 2 Dec 2014 10:52:27 +0000 From: Leon Alrae MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write accesses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Maciej W. Rozycki" , qemu-devel@nongnu.org Cc: Aurelien Jarno On 18/11/2014 03:59, Maciej W. Rozycki wrote: > Please note that for this validation I'm using an artificial microMIPS > processor that also has an FPU implemented, so that our microMIPS FP > support is correctly validated too (I don't really know if there exists > any real microMIPS processor that includes an FPU; if so, then it would > be good to add it to the list our supported configurations). FYI, there are real CPUs which support microMIPS and include FPU, for example microAptivUC. > qemu-mips-config3-isaonexc.diff Reviewed-by: Leon Alrae