From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH] KVM: cpuid: mask more bits in leaf 0xd and subleaves Date: Wed, 03 Dec 2014 09:04:30 +0100 Message-ID: <547EC40E.5010506@redhat.com> References: <1417525770-16485-1-git-send-email-pbonzini@redhat.com> <20141202230536.GA12980@potion.redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Wanpeng Li To: =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= Return-path: In-Reply-To: <20141202230536.GA12980@potion.redhat.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 03/12/2014 00:05, Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: > 2014-12-02 14:09+0100, Paolo Bonzini: >> - EAX=3D0Dh, ECX=3D1: output registers EBX/ECX/EDX are reserved. >=20 > (As good as reserved without XSAVES/IA32_XSS.) >=20 >> - EAX=3D0Dh, ECX>1: output register ECX is zero for all the CPUID le= aves >> we support, because variable "supported" comes from XCR0 and not XSS= =2E >> However, only bits above 0 are reserved. Output register EDX is res= erved. >=20 > (Yes. Well, EDX is 0 when the sub-leaf is invalid.) >=20 >> Source: Intel Architecture Instruction Set Extensions Programming >> Reference, ref. number 319433-022 >> >> Signed-off-by: Paolo Bonzini >> -- >> arch/x86/kvm/cpuid.c | 13 ++++++++++--- >> 1 file changed, 10 insertions(+), 3 deletions(-) >> >> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c >> index 0d919bc33b02..b1366743a728 100644 >> --- a/arch/x86/kvm/cpuid.c >> +++ b/arch/x86/kvm/cpuid.c >> @@ -470,10 +470,17 @@ static inline int __do_cpuid_ent(struct kvm_cp= uid_entry2 *entry, u32 function, >> goto out; >> =20 >> do_cpuid_1_ent(&entry[i], function, idx); >> - if (idx =3D=3D 1) >> + if (idx =3D=3D 1) { >> entry[i].eax &=3D kvm_supported_word10_x86_features; >> - else if (entry[i].eax =3D=3D 0 || !(supported & mask)) >> - continue; >> + entry[i].ebx =3D 0; >> + entry[i].ecx =3D 0; >> + } else { >> + if (entry[i].eax =3D=3D 0 || !(supported & mask)) >> + continue; >> + WARN_ON_ONCE(entry[i].ecx & 1); >> + entry[i].ecx &=3D 1; >=20 > ECX Bit 0 is set if the sub-leaf index, n, maps to a valid bit in t= he > IA32_XSS MSR and bit 0 is clear if n maps to a valid bit in XCR= 0. >=20 > ECX should be set to 0 instead, we definitely don't map to a valid bi= t > in IA32_XSS now. Well, there is a WARN just above. :) But I can change it to zero inste= ad. > (Having only one part of cpuid ready for it is weird ...) >=20 >> + } >> + entry[i].edx =3D 0; >> entry[i].flags |=3D >> KVM_CPUID_FLAG_SIGNIFCANT_INDEX; >=20 > (Unrelated, I have yet to understand how this flag translates > * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return = 0.) If the index is invalid, entry[i].eax is zero and we do not return anything at all. Paolo >> ++*nent; >=20 > Forcing a change of the XSAVES implementation is a likely purpose of > this patch and it is correct after changing the ecx handling, so then= , >=20 > Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99 >=20